Whitepaper: Electronics Cleanliness Testing

Estimated reading time: 5 minutes

Abstract

This study is an investigation and comparison of the performance of no-clean liquid wave soldering fluxes using a commercially available localized extraction and cleanliness testing system and surface insulation resistance (SIR) testing.

The flux test coupons for both tests were prepared in accordance with IPC TM-650 2.6.3.3. The IPC B-24 coupons used were manufactured using a lead-free wave solder process. Coupons were then tested for SIR per J-STD-004B using IPC TM-650 2.6.3.7 and tested with localized cleanliness testing.

The results for 15 no-clean fluxes are presented: three VOC-free rosin-free fluxes, two alcohol-based rosin-free fluxes, and 10 alcohol-based fluxes with rosin. The results with six of these fluxes were demonstrated in Part 1 of this study.

A divergence in test results is observed between the J-STD-004B SIR pass/fail requirement of 100 MÙ minimum and the clean/dirty results provided by the cleanliness test system.

The SIR resistance/time graphs and cleanliness tester current/time graphs are compared. The Corrosivity Index (CI) calculated based on the result of localized cleanliness testing is compared with final SIR values for the fluxes.

Introduction

Surface Insulation Resistance Tests

There are various test methods available for assessing SIR properties of no-clean flux residues, including those published by IPC, Bellcore, and Japanese Industrial Standards organizations. All SIR tests are accelerated electrochemical reliability prediction tests for no-clean fluxes that incorporate manufacturing conditions and service environment factors in the test methods. Although specific conditions can vary across the test methods, each test incorporates the following characteristics:

1. Test coupons utilizing comb patterns with defined comb width and spacing

2. Sufficient flux loading applied to each comb pattern

3. Coupons are processed in a wave solder system in both comb up (preheat without solder wave contact on the combs) and comb down (preheat and solder wave contact) orientations

4. Applied bias and exposure to accelerating fixed temperature and humidity environments

5. Quantified pass/fail minimum resistance criteria

6. Qualitative pass/fail inspection requirements after environmental conditioning

Localized Extraction and Cleanliness Testing

The commercially available cleanliness test system utilized in this study uses a novel localized extraction method to isolate the flux under test from a surface where flux has been applied. This system applies steam generated from deionized water and vacuum to extract a solution of flux residue and water. The steam head contains an integral PCB coupon that is immersed in the extracted solution. A bias is applied across a set of non-connected PCB lands and current across these lands is measured. The time for the current to reach a critical value called a “current leakage event” is measured. The system reports a clean result if the current remains below the critical value for a minimum specified time; otherwise, the test system reports a DIRTY result.

Test Methods

SIR Testing According to IPC J-STD-004B (Requirements for Soldering Fluxes)

IPC J-STD-004B 3.4.1.4 provides SIR test requirements for manufacturers of no-clean fluxes. This standard refers to IPC TM-650- 2.6.3.7 (Surface Insulation Resistance) for the specific conditions for performing this testing, requires a test duration of 7 days, and refers to IPC TM-650 2.6.3.3B (Surface Insulation Resistance, Fluxes) for preparation of the test coupons.

The above referenced test methods call for a number of conditions that are to be followed when performing SIR testing. The IPC B-24 test coupon is specified, with four comb patterns per coupon. Each individual comb pattern is unpreserved bare copper, with 0.4 mm width lines and 0.5 mm spacing between comb traces.

The test coupons used in this study are a modified version of the B-24 coupon that maintain the key characteristics on a slightly different form factor PCB.

The test conditions are specified as 40 ± 2°C and 90 ± 3% relative humidity. During the seven-day environmental conditioning exposure, a direct current bias of 25 ± 1 V/mm between adjacent parallel traces of the comb patterns is applied. This is equivalent to 12.5 ± 0.5 V on the B-24 coupon, having 0.5 mm comb spacing.

The key qualitative output of J-STD-004B SIR testing is the measurement of the resistance between adjacent comb patterns. These SIR measurements are taken at a maximum interval of 20 minutes over the environmental conditioning test duration.

The criteria for passing the SIR test are:

1. All SIR measurements between adjacent combs is no less than 100 MÙ (log SIR > 8) between hours 24 and 168 of the conditioning duration

2. There shall be no evidence of electrochemical migration that reduces conductor spacing by more than 20%

3. There shall not be corrosion of comb conductors

The visual inspections for electrochemical migration and corrosion after SIR testing are performed at 30–40X magnification in light field and dark field lighting.

Localized Extraction and Cleanliness Testing System

This test system utilizes a steam head to extract a sample of deionized water and flux residue effluent from a localized region of approximately 0.1 in2 (6.45 mm2). The test system is designed to extract the flux residue effluent by heating deionized water and delivering it to the test site, followed by a vacuum aspiration of the solution into the collection reservoir. This cycle is performed nine times to produce a volume of effluent sufficient to fill the collection reservoir to a point where the exposed traces on the test coupon are covered. The test system applies a known bias (10 VDC) across the test coupon electrodes and measures the resulting current every 0.25 seconds.

The test system provides for two different acceptance criteria schemes. The more stringent criteria are recommended for use on IPC Class 2 and Class 3 assemblies and the less stringent criteria are recommended for use on IPC Class 1 assemblies. It should be noted that no IPC specification refers to this test, and the selection of IPC classes as representative of the two test limits is arbitrary.

The Class 2/3 acceptability limit is a measured current below 250 μA for a minimum of 120 seconds. The Class 1 acceptability limit is a measured current below 500 μA for at least 60 seconds. For both conditions, test cycles that meet the acceptance requirements are reported as CLEAN and test cycles that do not meet the acceptance requirements are reported as DIRTY.

In addition, the localized cleanliness test system reports a measure that is called the Corrosivity Index (CI). The index is calculated by dividing the maximum current seen during the test by the elapsed time of the test, or by dividing the maximum test current limit by the time required to reach the limit.

The calculation for determining the CI for any test indicates that a lower CI is preferable. For reference, the Class 2/3 limit of 250 μA at 120 seconds can be converted to a CI of 2.08; this implies that a CI higher than 2.08 indicates a DIRTY test result for the Class 2/3 limit. The CI at the Class 1 limit of 500 μA at 60 seconds is 8.33.

To read the full article, which appeared in the August 2018 issue of SMT007 Magazine, click here.