Dissecting the IPC Regional Survey on PCB Technology Trends
July 15, 2019 | I-Connect007 Editorial TeamEstimated reading time: 21 minutes
Johnson: That’s a good point. For an OEM working on something fairly technical with complex circuitry that is destined to go to volume, you should expect that you’re probably not the only house in the design cycle. Then, once the OEM goes to volume, it will move overseas. That dynamic looks like that should still continue.
Holden: Well, you have to define “volume.” Most of the money in the volume electronics coming out of North American OEMs is not super high volume, and China realizes that. China is trying to learn how to get the smaller lot sizes because they already know who the big companies are, such as Apple and Samsung. They demand the lowest prices, so it’s a slim margin that you can only make any money out of enormously high volumes. But the majority of North American and European electronics is not high volume. It’s much more reasonable that people in Europe and North America can supply that volume at a competitive price.
Johnson: Sharon, in addition to the regional insights, is there any information in the report that you’d like to bring to the topic as we start winding down?
Starr: In terms of what PCB shops report that they’re capable of doing compared to what the OEMs are specifying, they seem to be in good shape. Their capabilities currently are exceeding the requirements of OEMs, and they expect that to continue out five years. That’s a promising finding.
Holden: Did the OEMs specify any future reduction or change in the pitch, especially from the wafer-level packaging people? Did they say anything about finer pitch coming?
Starr: Yes. For minimum I/O pitch for surface mount packages, the OEMs are predicting a slight decrease over the next five years. The PCB fabricators were anticipating a bigger decrease. But the PCB fabricators who responded were able to do a smaller I/O pitch than the OEMs were reported specifying. Again, that’s one of those areas where the PCB fabricators seem to be in good shape in relation to what the OEMs need.
Johnson: So, the challenge is not so much the geometries as it is the reliability.
Holden: If you underfill fine pitch, it is super reliable. Delphi has been putting flip-chip silicon directly on their circuit board for the last 12 years because, again, it’s reliable when it’s underfilled. But when applying the silicon directly to the circuit board without using an interposer or package, a space transformer bodes in that there would be more fine pitch. We’re talking about 0.3-, 0.25-, and 0.2-millimeter pitch, not just 0.5 or 0.4 millimeters.
Fritz: We picked that up in the survey. Again, the thing that bothers me is if you have an island of density, like GM has been able to do for 12 years now, does that relate to a general process change to mounting many silicon chips in some way to some substrate? An island of density is a term I heard 15 years ago.
Holden: I don’t think so. With CFX and the increasing number of people in surface-mount technology and pick-and-place equipment around the world jumping into it, they’re going to be able to place those pieces of silicon that are fine-pitched and small at the same speed that they can throw down resistors and capacitors. The only additional step is they have to underfill it, but they’ve been putting down adhesives for a long time.
It will be interesting. The semiconductor companies are hard to predict. What will they do? When it comes to wafer-level packaging or other sessions at conferences, they’re out in the hall and the atrium where it’s standing room only. Papers that talk about the elimination of the interposer and the package and coming directly off the silicon either by panel or wafer lower the overall cost. You have the five-cent chip on the five-dollar package problem.
Johnson: Is there any RF or high-frequency data to discuss before we finish?
Starr: We do have some data on maximum frequency. This was an OEM question specifically, and they’re anticipating a big increase in products that need to operate at higher frequencies.
Carano: With IoT and vehicle-to-vehicle communication, I have customers now building to 77 GHz. The reason they’re building to 77, besides the requirement, is because they can’t do any better than that because the material set that is out there from the laminators is not capable of doing 77 GHz yet. They’re trying to get to 100, but they’re not there yet.
One other regional difference worth noting is in the use of solderable or final finishes. In North America and Europe, you see a lot of ENIG and hot air leveling with the sprinkling of other finishes, including OSP, and silver and immersion tin. Overall, ENIG and hot air leveling are big. In Asia, OSP is the dominant finish because of the type of boards that are made and the end-use applications. ENIPEG is used over there, but it’s a small amount on the substrate side. ENIG is big in terms of square footage. I’m not talking about the money spent on it because it’s just an expensive finish, but in terms of square footage, it’s small compared to OSP. There are some significant regional differences being driven by the end-use application of the board. Where is it going to be used and under what conditions? That drives things like the finish.
Johnson: Thank you all for your time today.
Page 4 of 4Suggested Items
I-Connect007 Editor’s Choice: Five Must-Reads for the Week
07/11/2025 | Andy Shaughnessy, Design007 MagazineThis week, we have quite a variety of news items and articles for you. News continues to stream out of Washington, D.C., with tariffs rearing their controversial head again. Because these tariffs are targeted at overseas copper manufacturers, this news has a direct effect on our industry.I-Connect007 Editor’s Choice: Five Must-Reads for the Week
Digital Twin Concept in Copper Electroplating Process Performance
07/11/2025 | Aga Franczak, Robrecht Belis, Elsyca N.V.PCB manufacturing involves transforming a design into a physical board while meeting specific requirements. Understanding these design specifications is crucial, as they directly impact the PCB's fabrication process, performance, and yield rate. One key design specification is copper thieving—the addition of “dummy” pads across the surface that are plated along with the features designed on the outer layers. The purpose of the process is to provide a uniform distribution of copper across the outer layers to make the plating current density and plating in the holes more uniform.
Trump Copper Tariffs Spark Concern
07/10/2025 | I-Connect007 Editorial TeamPresident Donald Trump stated on July 8 that he plans to impose a 50% tariff on copper imports, sparking concern in a global industry whose output is critical to electric vehicles, military hardware, semiconductors, and a wide range of consumer goods. According to Yahoo Finance, copper futures climbed over 2% following tariff confirmation.
Happy’s Tech Talk #40: Factors in PTH Reliability—Hole Voids
07/09/2025 | Happy Holden -- Column: Happy’s Tech TalkWhen we consider via reliability, the major contributing factors are typically processing deviations. These can be subtle and not always visible. One particularly insightful column was by Mike Carano, “Causes of Plating Voids, Pre-electroless Copper,” where he outlined some of the possible causes of hole defects for both plated through-hole (PTH) and blind vias.
Trouble in Your Tank: Can You Drill the Perfect Hole?
07/07/2025 | Michael Carano -- Column: Trouble in Your TankIn the movie “Friday Night Lights,” the head football coach (played by Billy Bob Thornton) addresses his high school football team on a hot day in August in West Texas. He asks his players one question: “Can you be perfect?” That is an interesting question, in football and the printed circuit board fabrication world, where being perfect is somewhat elusive. When it comes to mechanical drilling and via formation, can you drill the perfect hole time after time?