Defense Speak Interpreted: Is DARPA Still Around After CHIPS?
Beyond the Board: Orbital High Ground—Why Space Superiority Is Slipping Away
The Government Circuit: Trump’s Trade War Disrupts the Electronics Ecosystem
Advancement of SPI Tools to Support Industry 4.0 and Package Scaling
August 6, 2019 | A. Prasad, L. Pymento, S.R. Aravamudhan, and C. Periasamy, Intel Corp.Estimated reading time: 13 minutes
Another point to be noted is that the majority of these tools (except A+ and B) employ Z-height threshold >10 um to estimate. They ignore the height and volume of the metal pad in the solder paste deposit calculation. For large volume deposits, metal pad volume contribution will be small and may not affect accuracy bias as much. Software algorithms and implementations can vastly vary from vendor to vendor. It is clearly evident that threshold-free measurements, along with correct hardware, is more accurate for low-volume solder paste deposits.
Figures 7a and b: Variability chart for bias % for Phase 3 volume range.
Conclusions and Recommendations
The results of the study showed increased sensitivities to low solder deposits of less than 250 cubic mils across SPI equipment employing threshold algorithm values >10 µm and spatial resolution ≥7 µm. Evaluations on a 5-µm resolution system (A+ tool) employing 0-µm threshold algorithms were found to have acceptable accuracy deviations of less than ±20%.
To improve inline SPI accuracy for low solder paste volume deposits, SPI vendors must consider calibration of SPI tools with lower-volume (below 200 cubic mils) NIST or equivalent standards. For fine-pitch applications, as well as lines configured for Industry 4.0, accuracy should be a consideration for SPI tool selection.
Acknowledgments
The authors would like to acknowledge the Intel internal team and the engineering teams at various SPI vendors for their help in completing the SPI measurements and answering inquiries about the tool capabilities.
References
- C. Shea, and R. Farrell, “Stencil and Solder Paste Inspection Evaluation or Miniaturized SMT Components,” Proceedings of SMTA International, 2013.
- J. M. Peallat, “New Opportunities for 3D-SPI,” www.circuitnet.com, 2008.
- CyberOptics, “‘True’ Heights Measurement in Solder Paste Inspection (SPI),” www.cyberoptics.com, 2013.
- H. Biemans, “5D Solder Paste Inspection: Merits Beyond 3D Technology,” Global SMT & Packaging, 2011.
- C. Periasamy, and S. Walwadkar, “A Scanning Chromatic Confocal Microscope for Accurate Off-Line Solder Paste Volume Measurement,” Proceedings of SMTA International, 2017.
- Intel internal survey report.
This paper was originally presented at the Technical Proceedings of SMTA International 2018.
Authors
Abhishek Prasad is a process engineer at Intel Corporation.
Larry Pymento is a senior process/technology development program manager at Intel Corporation.
Srinivasa R. Aravamudhan is a process technology development engineer at Intel Corporation.
Chandru Periasamy is a packaging R&D engineer, metrology and mechanics, at Intel Corporation.
Page 3 of 3Share on:
Suggested Items
Knocking Down the Bone Pile: Tin Whisker Mitigation in Aerospace Applications, Part 3
06/25/2025 | Nash Bell -- Column: Knocking Down the Bone PileTin whiskers are slender, hair-like metallic growths that can develop on the surface of tin-plated electronic components. Typically measuring a few micrometers in diameter and growing several millimeters in length, they form through an electrochemical process influenced by environmental factors such as temperature variations, mechanical or compressive stress, and the aging of solder alloys.
SolderKing’s Successful Approach to Modern Soldering Needs
06/18/2025 | Nolan Johnson, I-Connect007Chris Ward, co-founder of the family-owned SolderKing, discusses his company's rapid growth and recent recognition with the King’s Award for Enterprise. Chris shares how SolderKing has achieved these award-winning levels of service in such a short timeframe. Their secret? Being flexible in a changing market, technical prowess, and strong customer support.
Preventing Surface Prep Defects and Ensuring Reliability
06/10/2025 | Marcy LaRont, PCB007 MagazineIn printed circuit board (PCB) fabrication, surface preparation is a critical process that ensures strong adhesion, reliable plating, and long-term product performance. Without proper surface treatment, manufacturers may encounter defects such as delamination, poor solder mask adhesion, and plating failures. This article examines key surface preparation techniques, common defects resulting from improper processes, and real-world case studies that illustrate best practices.
Breaking Silos with Intelligence: Connectivity of Component-level Data Across the SMT Line
06/09/2025 | Dr. Eyal Weiss, CybordAs the complexity and demands of electronics manufacturing continue to rise, the smart factory is no longer a distant vision; it has become a necessity. While machine connectivity and line-level data integration have gained traction in recent years, one of the most overlooked opportunities lies in the component itself. Specifically, in the data captured just milliseconds before a component is placed onto the PCB, which often goes unexamined and is permanently lost once reflow begins.
BEST Inc. Introduces StikNPeel Rework Stencil for Fast, Simple and Reliable Solder Paste Printing
06/02/2025 | BEST Inc.BEST Inc., a leader in electronic component rework services, training, and products is pleased to introduce StikNPeel™ rework stencils. This innovative product is designed for printing solder paste for placement of gull wing devices such as quad flat packs (QFPs) or bottom terminated components.