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Trouble in Your Tank: Via Hole Filling and Plugging, Part 1

High-density interconnect (HDI) demands that vias that do not contain component leads be plugged with either a polymeric paste or electroplated copper. In this column, the technology drivers for via filling/plugging in the context of HDI are presented.

Performance-driven electronic systems continue to challenge companies in seeking a more innovative semiconductor package methodology. The key market driver for semiconductor package technology is to provide greater functionality and improved performance without increasing package size. As semiconductor die elements shrink in size, companies are seeking to further increase package density and enhance functional performance. This, in turn, drives designers to expand the current role of the interposer to interconnect both heterogeneous logic functions and homogeneous memory within a single package outline.

The package interposer is the key enabler; this is especially true as glass-reinforced, epoxy-based materials, and high-density copper interconnect capability will continue to carry a primary role for array configured packaging. From a PCB fabrication standpoint, engineers must adopt the manufacturing processes to include via fill and via plugging technology. I will dive into details of these processes over the next few editions of “Trouble in Your Tank.” However, this particular column will focus on the need for via filling and some of the methods used to carry out the process.

Why Fill Vias?

Microvias, buried vias, and plated through-holes are filled with conductive or non-conductive materials for a number of reasons:

• Improved reliability (avoidance of trapped air or liquids)

• Improved planarity of multilayer structures (for more reliable surface mount or improved photolithography)

• Higher interconnect density (e.g., via-in-pad vs. dog bone designs, Figure 1)

• Better thermal management

• Density, density, density

• Increased I/O number for packaging applications

• Minimized signal delays and to avoid defects associated with electromigration

• Enables stacked microvia structures (often seen in smartphones’ board technology, Figure 2)

Figure 1: Via-in-pad versus dog bone design.

Figure 2: Component mounted on unfilled vias (note the air pockets).

Via-in-pad reduces the footprint as well as increases the density. This design concept places the via directly below the component contacts and reduces the footprint when compared to fan-out. When via-in-pad is used in a design, there will be the call-out for via filling or plugging process (more on the process options for via filling in a future column). Filling the via that is in the pad will improve the bond strength of the component when mounted over the filled via (Figure 2).

The concern with the issue shown in Figure 2 is that air inclusions during the lamination process may reduce long-term reliability. An additional concern with air inclusions is that, in effect, air is an insulator. Thus, air reduces both electrical and thermal conductance. While it is acceptable to endure very small voids in the via simply due to processing and material properties, it is desirable to minimize air voids through material property selection, via plugging techniques, and equipment designs [1].

In the next few columns, I will present overviews of the different via fill technologies available. Meanwhile, one must first understand the definitions used for via fill and/or via plugging. While this distinction may seem trivial, it must nonetheless be clearly communicated between the board supplier and end user (as agreed between user and supplier, or AABUS).

To read the full article, which appeared in the August 2019 issue of PCB007 Magazine, click here.