Additive Electronics Conference Set for October 2019 Debut

Estimated reading time: 9 minutes

Kelly Dack and Tara Dunn talk about the upcoming conference "Additive Electronics: PCB Scale to IC Scale" on October 24, 2019, hosted by SMTA in San Jose, California, and why it’s an important event for people to attend—especially those involved in the design process. 

Kelly Dack: I’ve heard a lot recently about additive electronics, and I’m familiar with the subject only from the standpoint of 3D printers layering up different materials, including conductive materials. But a couple of weeks ago, I reconnected with Tara Dunn who talked to me about the Additive Electronics Conference that’s coming up, which will cover a very different realm. My perception was that this particular context of additive electronics is more of a micro-scale take on finished copper. We discussed seeing copper on a very small scale, which can build circuitry in the range of three-thousandths of an inch all the way down to five microns. I am excited and want to know more about it. Tara, can you tell us what this conference is about?

Tara Dunn: We’re looking for different options to attack the market segment that is sub-75-micron trace and space all the way down to the 5-micron trace-and-space range. This is that gap area between PCB manufacturing and IC fabrication.

Dack: That’s sounds very interesting. Would this be considered cutting-edge or uncharted territory for most PCB designers and engineers?

Dunn: Definitely. People being introduced to the technology will often ask, “What are the design rules?” The blunt answer is there are really aren’t design rules just yet; everything is still developing quickly, and the designs tend to be much more collaborative than we’re used to with traditional PCB design rules. For instance, somebody may come to us and say, “I have this idea, I need this type of material, and I’m trying to accomplish this. How can we go about it?” Tt becomes a brainstorming session. How can we use the technology that we have today in different ways to figure out how to solve the problem? 

One of the things we’re hoping to do at the conference is spark a lot of ideas. We want to provide a lot of opportunities for people to let their imagination kick into gear and think, “This person is using this technology this way; how might I be able to apply that?” We want it to be very interactive.

Dack: This is a really good subject for designers. As a designer myself, and having designed lots and lots of flex circuitry, I have learned what you can’t do by making mistakes—especially with copper. Over the years, a designer learns that there are types of processed copper. The copper thickness and grain structure must be considered along with conductor layer topology. Trace or conductor widths are critical not only in considering electrical performance but also in manufacturability. That criticality has to do with the subtractive process of the way we etch copper circuitry onto flex material or any other type of material.

With a subtractive or chemical etching process, there’s a trace structure that based on the height or thickness of the copper foil and relative to the trace width. If a designer isn’t properly considering conductor height to width formulas, the nominal design data—if not addressed by a supplier in CAM—could etch away the base of the copper conductor because of the unique way conductors etch in the tank. 

Now, with the additive process, my understanding is that there’s no etch factor. Therefore, the limitations are only in how thin the copper can be printed. At the point that seed copper is printed or imaged onto a surface, the conductors can be grown from that copper, and the cross-section of the conductor doesn’t take on this strange trapezoidal shape as it does during a print and etch cycle; instead, it forms a rectangular shape or thereabouts. Is that true?

Dunn: Yes. There are a couple of different technologies that have received a lot of publicity within the last couple of years, which were triggered by the news that many of the current smartphones are using the modified semi-additive process in very high volume, offshore. Now, we’re looking at having similar technology to mSAP or a semi-additive process here domestically with low-volume and development-type work.

The basic idea behind these two processes is that you start with a very thin seed layer of copper, and that’s usually the key: the thinness of that copper, whether you’re using a very thin copper foil or putting a seed layer of copper down chemically. Then, it becomes an imaging process. You apply your resist, do your imaging, and then use electrolytic copper to plate the traces up to the desired width that you’re looking for. And you’re right, Kelly; because we’re not subtractively etching the trace will straight up and down, there will be no trapezoidal effects. There are RF benefits, in addition to the advantages of space, weight, and packaging. From that point on, these processes are run through PCB fabrication with the same processes used for subtractive etch today.

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