It’s Only Common Sense: Selling to Today's Generation of Buyers
Dan’s Biz Bookshelf: ‘Believe in Better'
The Big Picture: Our Big ‘Why’ in the Age of AI
Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications
December 10, 2019 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Global Unichip Corporation (GUC) successfully deployed the Cadence® digital implementation and signoff flow and delivered advanced-node (N16, N12 and N7) designs for artificial intelligence (AI) and high-performance computing (HPC) applications. Through use of the Cadence Innovus™ Implementation System and the Voltus™ IC Power Integrity Solution, GUC achieved first-pass silicon success and met its GHz performance target for its multi-billion gate designs.
Traditional digital implementation and signoff tools lack the capacity GUC required for their multi-billion gate designs during the implementation and signoff stages. Alternative solutions on the market must be greatly scripted because they don’t offer a shared data model-level integration, requiring more manual work with increased design margins and limited performance. Where the traditional tools fall short, the tightly integrated Cadence solution helped GUC meet power, performance and area (PPA) targets and deliver their large-capacity, advanced designs on time.
The Innovus Implementation System improved the GUC design team’s productivity through its efficient hierarchical partitioning flow, advanced top-level floorplanning and block implementation and closure capabilities. The Voltus IC Power Integrity Solution enabled GUC to accurately analyze the top-level full-chip static/dynamic power, IR drop and electro-migration through its distributed processing capability using innovative extensive parallelism technology. The seamless shared data model-level integration between the Cadence tools provides GUC with an efficient way to close signoff EM-IR issues during block implementation, reducing costly iterations and engineering change orders (ECOs).
“As a leader in ASIC design, we need to deliver highly complex designs to customers quickly, particularly for emerging application areas like AI and HPC,” said Louis Lin, senior vice president of Design Services at GUC. “Through our deep collaboration with Cadence, we deployed their digital implementation and signoff tools quickly and easily, and the Cadence team also provided prompt support to further optimize our delivery cycle time and achieve our PPA targets.”
The Cadence Innovus Implementation System and Voltus IC Power Integrity Solution are part of the broader digital implementation and signoff full flow and provide customers with a faster path to design closure. The tools in the flow support the company’s Intelligent System Design™ strategy, enabling advanced-node system-on-chip (SoC) design excellence for AI and HPC applications.
Share on:
Suggested Items
DownStream Acquisition Fits Siemens’ ‘Left-Shift’ Model
06/26/2025 | Andy Shaughnessy, I-Connect007I recently spoke to DownStream Technologies founder Joe Clark about the company’s acquisition by Siemens. We were later joined by A.J. Incorvaia, Siemens’ senior VP of electronic board systems. Joe discussed how he, Rick Almeida, and Ken Tepper launched the company in the months after 9/11 and how the acquisition came about. A.J. provides some background on the acquisition and explains why the companies’ tools are complementary.
Elementary Mr. Watson: Retro Routers vs. Modern Boards—The Silent Struggle on Your Screen
06/26/2025 | John Watson -- Column: Elementary, Mr. WatsonThere's a story about a young woman preparing a holiday ham. Before putting it in the pan, she cuts off the ends. When asked why, she shrugs and says, "That's how my mom always did it." She asks her mother, who gives the same answer. Eventually, the question reaches Grandma, who laughs and says, "Oh, I only cut the ends off because my pan was too small." This story is a powerful analogy for how many PCB designers approach routing today.
Siemens Turbocharges Semiconductor and PCB Design Portfolio with Generative and Agentic AI
06/24/2025 | SiemensAt the 2025 Design Automation Conference, Siemens Digital Industries Software today unveiled its AI-enhanced toolset for the EDA design flow.
Cadence AI Autorouter May Transform the Landscape
06/19/2025 | Andy Shaughnessy, Design007 MagazinePatrick Davis, product management director with Cadence Design Systems, discusses advancements in autorouting technology, including AI. He emphasizes a holistic approach that enhances placement and power distribution before routing. He points out that younger engineers seem more likely to embrace autorouting, while the veteran designers are still wary of giving up too much control. Will AI help autorouters finally gain industry-wide acceptance?
Beyond Design: The Metamorphosis of the PCB Router
06/18/2025 | Barry Olney -- Column: Beyond DesignThe traditional PCB design process is often time-consuming and labor-intensive. Routing a complex PCB layout can consume up to 30% of a designer’s time, and addressing this issue is not straightforward. We have all encountered this scenario: You spend hours setting the constraints and finally hit the Go button, only to be surprised by the lack of visual appeal and the obvious flaws in the result.