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Improving Copper Distribution in Pattern Plating Using Simulation Software
April 28, 2020 | Pete Starkey, I-Connect007Estimated reading time: 1 minute
DFM guidelines may offer some qualitative rules about aiming for uniformity of copper distribution within a layer and maintaining symmetry in a stackup, but generally, these refer to inner-layer copper and relate to avoiding pressure differentials in the laminating press and bow-and-twist in the reflow oven.
What about the outer layers if the design is to be manufactured by pattern plating, particularly if conductor cross-sections and plated-through-hole finished diameters are critical? Does the PCB designer understand the principles of pattern electroplating? Circuit features in sparsely populated areas will take more than their nominal share of the deposited copper.
And what about panelisation? Is the design required to be delivered as a multiple on an assembly panel? Or is it cost-effective to manufacture only if incorporated into a multi-image production panel—whether of the same design or a mixture of designs?
From the point of view of the PCB fabricator, it is clearly bad practice to interfere with a customer’s design by adding balancing copper as non-functional areas within the layout, unless this is done in consultation with the designer and formally approved before the design is signed-off.
But on a panel, balancing copper—alternatively termed “copper thieving”—may be legitimately added to the panel border and in the spaces in between individual boards in order to improve the uniformity of electroplated copper thickness distribution by effectively stealing some of the plating current that would otherwise tend to be concentrated on sparse features.
From a production standpoint, if the individual boards in a multi-image panel have an uneven copper distribution, or if two or more designs are incorporated in the panel, there could be some benefit in arranging their relative positions and orientations to improve the uniformity of electroplating. Maybe counterintuitively, the yield might be improved by putting fewer images on the panel with more space between them to allow for thieving.
To read this entire article, which appeared in the April 2020 issue of PCB007 Magazine, click here.
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