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Happy’s Tech Talk #1: Vertical Conductive Structures (VeCS)

In remembrance of our late technical editor Dr. Karl Dietz, Happy Holden has volunteered to resurrect Karl’s popular Tech Talk column. Karl authored this technical column from August of 1995 to August of 2016 compiling 225 insertions over those 21 years. Happy will endeavor to catch our readers up on the latest technologies developed around the world and close the five-year ‘gap’ since Karl stopped writing his column. Karl passed away in 2020.

The industry has not introduced many new structures in the last 60 years. Multilayers have continued to evolve with thinner materials and smaller traces and spaces as well as drilled vias. It’s been nearly 40 years since Hewlett-Packard put its first laser-drilled microvia boards into production for its innovative Finstrate process¹. 

Now we have a new structure, vertical conductive structures (VeCS), developed by Joan Tourné of NextGIn Technology BV of the Netherlands. This technology is a breakthrough because now any advanced board shop can produce HDI level high density interconnects without any new capital equipment—and at a lower cost with higher electrical performance. I first became aware of the technology from an interview in the February 2017 issue of The PCB Magazine². As seen in Figure 1, the key technology is the replacement of small or blind vias with a routed trench (slot), that is much easier to metallize and plate.

Figure 1: VeCS slot under magnification (left), bottom view of VeCS slot (right). (Source: NextGIn)

VeCS is a true 3D concept for interconnection by creating a routing channel (slot) in the printed circuit that can then be metallized and plated easier than high-aspect ratio vias while allowing a connection to the inner layers. The channels are easier to plate and can be created by existing PCB fabrication equipment. This allows HDI densities to be achieved without significant added costs along with easier fabrication processes and higher electrical performance and reliability. The process and applications already developed by NextGIn Technologies are: VeCS -1, -2, and -HDI^2,3. The three main combinations of their interconnect slot technology are defined as:

• VeCS-1: Where the channel (slot) goes through the substrate
• VeCS-2: Here, the slot is formed as blind or in a hybrid-blind and through-slot combination
• VeCS-HDI: Laser-drilled microvias are used for fine-pitch utility on ultra-fine-pitch components

Figure 2 highlights these three structures.

Figure 2: (Left) Three different structures, based on the original concept of a slot or trench, make up VeCS; (right) trace routes showing various layers, and 3D views of the construction. (Source: NextGIn)

With channels (slots) formed from both sides, the 3D vertical traces provide greatly increased density without sequential laminations. Replacing larger through-hole vias with slots provides better power integrity for new power-hungry chips while lowering inductance and capacitance for improved signal integrity.

The Channel or Slot
The all-important step of metallizing and plating the typical 0.3 mm blind slot is shown in Figure 3. for various depths and lengths (from depths of 0.47 mm to 1.23 mm and lengths of 0.6 mm to 1.8 mm). Some of the smaller aspect ratios have insufficient chemical exchange but the majority have excellent chemical exchange for normal plating baths. The new alternative drill/router bits have successfully created channels of 0.1 mm with straight walls and no burring. Figure 3 shows various blind channel depths plated with conventional plating equipment.  

Figure 3: Creating and plating the blind channel (slot) is the key feature of VeCS-2 but is within the capability of any high-performance PCB fabricator³.

Figure 4³ shows plating results with respect to the slot length and slot depth. Note that for these tests, NextGIn used plating processes at standard parameters and chemistry types. The method of plating was electroless copper followed by a pan-el plate to the required copper thickness in the slot targeting a thickness of 25 µm.

Fabrication Process
Figure 5 presents the views of the VeCS fab process, starting with a conventional through-hole multilayer. The process has eight steps:

1. Create slot
2. Plate slot
3. Alignment in BGA pin field
4. Resin fill PR slot and PR stencil
5. Drill CR slots
6. If vertical traces are going to be used, drill BR slots
7. BR/CR stencil
8. Resin fill BR/CR slot

In Step 1, after drilled vias are completed, the primary cross-rout (CR) slots are put in. Here, a special drill/router bit uniquely suited for this operation is used. Much work and experimentation were conducted to perfect an ideal drill/router bit for this task. Then in Step 2, metallization and copper plating are performed. In Steps 3 and 4 the resin is now used to fill the CR slots. After curing, next is the important Step 5 where cross-routes create the vertical interconnects. If vertical traces are going to be used, Step 6, drill/rout out the back-rout (BR) slots. Then selected vias and slots are resin-filled and cured. In Steps 7 and 8, for pattern plating, the normal process resumes of imaging, plating, stripping and final etching. In the final panel, the board would be solder masked, with any final finishes and fabrication.

Figure 5: The VeCS fabrication eight-step process⁸. (Source: NextGIn)

Design Rules
To illustrate various routing densities, we like to illustrate 0.7 mm pitch because VeCS has a 600% increase over through-hole while HDI has only a 200% improvement.

The cross-rout or CR step is also completed. Clearly you can see the glass dielectric removed between the VeCS circuits. This eliminates glass influence for issues like CAF⁴.

VeCS-2 design details: The middle part (conductive material) is removed to create two different potentials to the left and right of the slot. Not every position in the slot needs to be processed in this way as it depends on the design.

This design method for VeCS is another example of creative concepts. The VeCS-1 with back rout or VeCS-2 differential signals are routed and surrounded by a “racetrack” type ground reference. This nearly creates a complete Faraday Cage for the connections. The SI performance is beneficial for speeds above 10Ghz.

Details of the 0.5 mm pitch VeCS breakout using standard VeCS design rules are in referenced in Table 1. Routing will depend on cross-rout slot dimensions. But remember: HDI can only go one or two layers down, while VeCS can go three times deeper.

A complete set of design guidelines for VeCS-1 and VeCS-2 (Table 1) are broken down into standard, advanced, and in R&D. Additional design illustrations and advice, including tool setups are in the August 2019 issue of PCB007 Magazine⁵.

Videos that show the routing of VeCS structures on various EDA tools like Siemens/Mentor, Cadence, Zuken, and Altium are available by contacting NextGIn Technologies.

Electrical Performance
Electrical performance is another area (besides CapEx and costs) where VeCS outperforms plated through-hole and HDI. The vertical trace does not have the capacitance and inductance of a via. For extremely high-speed logic, the ability to create shielded differential pairs with minimum distortion is unique. As seen in Figure 7, experimentation was conducted to tune vertical traces in the slot such that there is almost no reflection/dispersion. BestPCB compared simulated vs. actual product measurements. Additional figures show the simulated tuning of a TDR response on VeCS-2 where we can vary it from a capacitance to an inductance response or make it as “flat” as possible on the NextGIn website.

Modeling with Simbeor has determined the best performing layer transition. Can we use VeCS to make layer transitions and re-introduce Manhattan routing? First results look interesting. Manhattan/VeCS routing is an alternative for expensive point-to-point routing for dense boards. VeCS electrical performance is discussed in an October 2019 PCB007 Magazine article⁶. (It contains an eye diagram showing simulated layer transition in VeCS at 30 GB/s.)

Reducing reflections in transmission lines is one of the areas of focus with VeCS. Tuning the impedance of the vertical trace using, for example, a shielded VeCS slot enables the designer to match the vertical and horizontal impedances of the transmission line. 

Figure 7: A TDR comparison of a high-speed signal propagation (impedance) through vertical connections of a back-drilled PTH versus a back-drilled VeCS-1 vertical trace seen in Fig. 7b. (Source: BestPCB)

Reliability
A VeCS laminate reliability review reported that on testing 370HR, it passed six cycles of 260°C reflow including CAF tests. IST VeCS coupons passed 250 cycles and 19 reflow cycles to 217°C. TCT performance on IST passed 100 cycles and TCT performance on CAF coupons passed 100 cycles (Figure 8a).

Extensive IST testing has revealed that VeCS coupons achieved 10 to 30 cycles while conventional PTH had a range of seven to 10 cycles (Figure 8b). Additional data is available from NextGln.

Figure 8: a) CAF test of three VeCS structures for 1090 hours at 85% RH, 850C at 100 volts; b) resistance change of five VeCS-2 slot structures for 500 cycles of 25 to 150°C (Source: WUS Printed Circuit Co.)

Future Enhancements
The current focus is on the use of HDI microvias to enable VeCS applications for fine pitches down to 0.15 mm. The micro-VeCS process is shown in Figure 9 for inner layers.  

Figure 9: The micro-VeCS process as follows: a) laser cutting the cavity; b) plating the cavity; c) apply positive electrodeposited resist; d) direct expose the resist; e) etch and strip; f) fill VeCS slot. 

VeCS/HDI will scale down the feature sizes for VeCS to enable it to run smaller devices pitches–device pitches down to 0.15mm are possible, as seen in Figure 10.

The benefits of VeCS/HDI are:

• No materials limitations. Use flat weave materials to support the laser processing
• Compete with HDI constructions and take advantage of reduced lamination cycles reducing lead time and complexity
• Single lamination process versus 5 or more laminations
• Reduce cost by 40-60%
• Higher yields

Figure 10: Routing of a very-fine pitch BGA using HDI, and VeCS-2 buried slots with close-up of quarter-pattern. (Source: NextGIn Technologies)

Additional information is available at PCB007, EIPC Winter Conference, and LinkedIn^7,8,9 and by contacting NextGIn Technologies.

References

1. “Finstrate: A New Concept in IC Substrates,” Steve Leishman, IPC Seminar on Competitive Electronics Packaging, October 1983, Washington, D.C.
2. “Vertical Conductive Structures—a New Dimension in High-Density Printed Circuit Interconnect,” Pete Starkey, The PCB Magazine, February 2017, pp. 16-20.
3. “Vertical Conductive Structures, Part 1: Rethinking Sequential Lamination,” Joan Tourné, PCB007 Magazine, April 2019, pp. 88-93.
4. “Vertical Conductive Structures, Part 2: VeCS and Micro-machining,” Joan Tourné, PCB007 Magazine, June 2019, pp. 72-78.
5. “Vertical Conductive Structures, Part 3: Design Tool Techniques,” Joan Tourné, PCB007 Magazine, August 2019, pp. 90–99.
6. “Vertical Conductive Structures, Part 4: Tuning Your Signal Performance,” Joan Tourné, PCB007 Magazine, October 2019, pp. 68­–76.
7. Vertical Conductive Structures, Joan Tourné, EIPC Winter Conference 2020 presentation.
8. “The Impact and Benefits of VeCS Technology,” an interview with Joan Tourné and Joe Dickson, PCB007 Magazine, November 2020, pp. 30-43.
9. VeCS-New High-Density Interconnects, Joe Dickson, Linkedin, November 2020.

Happy Holden is an I-Connect007 technical editor, and the author of 24 Essential Skills for Engineers.

This column originally appears in the October 2021 issue of PCB007 Magazine.