Cadence Wins Four 2021 TSMC OIP Partner of the Year Awards
November 15, 2021 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc. announced that it has won four Open Innovation Platform® (OIP) Partner of the Year awards from TSMC for their core EDA, IP and systems solutions. Cadence achieved recognition for the Joint Development of 4nm Design Infrastructure, 3DFabric™ Design Solution, Cloud-based Productivity Solution and DSP IP.
Cadence achieved these recognitions based on collaborative work with TSMC:
4nm design infrastructure: Cadence worked closely with TSMC to optimize the complete, integrated digital flow for the TSMC N4 process to help customers achieve power, performance and area (PPA) goals and speed time to market. In addition, Cadence delivered a comprehensive custom, analog, EM-IR and mixed-signal design solution, addressing the challenges and complexities for designing custom and analog IP on the TSMC N4 process.
3DFabric design solution: Cadence collaborated with TSMC to ensure that the new Cadence® Integrity™ 3D-IC platform, the industry’s first unified platform for 3D-IC planning, implementation and system analysis, is enabled for the TSMC 3DFabric™, a comprehensive family of 3D silicon stacking and advanced packaging technologies. Cadence Tempus™ Timing Signoff Solution has also been enhanced to support a new stacking static timing analysis (STA) signoff methodology, shortening design turnaround time.
Cloud-based productivity solution: Cadence delivered the Tempus Timing Signoff Solution with a cloud-ready distributed static timing analysis (DSTA) architecture with giga-scale techniques that let designers quickly optimize the best cloud configuration to balance wall time and cost.
DSP IP: Cadence worked with TSMC’s Soft IP9000 team to certify Cadence Tensilica® DSP IP in the TSMC integration flow.
“Over the course of many years, we’ve worked closely with Cadence to ensure our mutual customers have access to the latest technologies needed to innovate and achieve the best possible design results,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “The TSMC OIP Partner of the Year awards show that our ecosystem partners are committed to enabling customer success, and we look forward to seeing our customers leverage our advanced technologies to stay in front of the competition in their respective markets.”
“By continuing to collaborate with TSMC, we’re enabling mutual customers to deliver designs with confidence and meet design goals by leveraging our newest technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “These prestigious TSMC awards highlight Cadence’s dedication to enabling SoC design excellence via our Intelligent System Design strategy, and we are committed to continue innovating to ensure our customers have the tools they need to create emerging mobile, automotive and hyperscale computing applications and more.”
Suggested Items
Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
06/05/2025 | Cadence Design Systems, Inc.Cadence announced IP, design solution, and expert design services for software and Systems-on-Chip (SoCs) based on Arm® Zena™ Compute Subsystems (CSS), Arm’s first-generation CSS for automotive.
Cadence, AVCC to Advance Physical AI Innovations for Autonomous Vehicles
05/12/2025 | Cadence Design SystemsCadence has joined the Autonomous Vehicle Computing Consortium (AVCC), marking a significant step forward in Cadence's commitment to advancing autonomous vehicle technology for the physical AI era by working with industry leaders to define high-performance computing (HPC) and safety solutions for next-generation autonomous vehicle systems.
Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
05/01/2025 | Cadence Design SystemsCadence announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence® digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK).
Cadence Reports Q1 2025 Financial Results
04/29/2025 | Cadence Design SystemsQuarter-end backlog was $6.4 billion and current remaining performance obligations ("cRPO"), contract revenue expected to be recognized as revenue in the next 12 months, was $3.2 billion
Cadence Enables Next-Gen AI and HPC Systems with Industry’s Fastest HBM4 12.8Gbps IP Memory System Solution
04/21/2025 | Cadence Design SystemsCadence announced the industry’s fastest HBM4 12.8Gbps memory IP solution, which meets the increasingly higher memory bandwidth needs of SoCs targeted for the next generation of AI training and HPC hardware systems.