Synopsys Full EDA Flow First to Achieve Samsung Foundry 4LPP Process Certification

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Exemplifying a commitment toward accelerating the development of power-efficient, advanced-node chips, Synopsys, Inc. announced that its full EDA flow has been certified by Samsung Foundry for its new 4LPP (4nm Low Power Plus) process. The 4LPP process, which is available now, represents the latest implementation of Samsung Foundry's unique FinFET technology, which delivers chip density, performance and power advantages for SoCs fueling some of today's most in-demand applications, including high-performance computing, AI, and 5G infrastructure.

The Synopsys solutions certified for Samsung Foundry's 4LPP process encompass the full digital, analog and mixed-signal implementation and signoff flow. In addition, collaboration between the two companies has resulted in the availability of Synopsys 3DIC Compiler solution for the Samsung Foundry Multi-Die Integration (MDI™) flow, which is proven on 4LPP technology. 3DIC Compiler is a full exploration-to-signoff 3D solution to manage the complexity of hundreds of billions of transistors, while driving power, performance and area (PPA) per cubic mm silicon optimization. Synopsys is also developing a portfolio of DesignWare® Foundation IP and Interface IP that delivers low latency, high bandwidth and power efficiency for chips developed on the 4LPP process.

"Samsung Foundry is pleased to have worked closely with Synopsys to ensure readiness of its full EDA flow for our 4LPP process," said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. "Synopsys is an ideal partner to join forces on pathfinding efforts to facilitate new-node enablement as we further advance our roadmap on new technologies such as our upcoming 3nm gate-all-around process."

As the first EDA vendor to achieve full-flow certification for the 4LPP process via the SAFE-QEDA program, Synopsys is poised to accelerate a smooth adoption process for customers, minimizing risk and reducing turnaround time and costs. The SAFE-QEDA program is designed to mitigate risks of new node adoption.

"Our close collaboration continues to accelerate technology advances to drive innovation in high-performance computing, AI accelerators, AR/VR and other popular application areas," said Shankar Krishnamoorthy, GM and corporate staff for the Silicon Realization Group at Synopsys. "The certification of our platforms for Samsung Foundry's 4LPP process ensures the highest level of silicon correlation and design robustness to enable chipmakers to realize best-in-class PPA and faster turnaround times."