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Happy's Tech Talk #4: Semi-Additive Processes and Heterogeneous Integration

The semi-additive processes (SAP) are not new. I first used them with a novel process back in 1978. MacDermid had a novel SAP process called PLADD II (plated additive). It was an anodized aluminum foil applied to laminates that we could easily etch off after drilling and continue with a special electroless copper for thin metallization.

In his Tech Talk column, Karl Dietz wrote about SAP many times from 2000 to 2010.^1-5 In a 2010 column, Karl included a table (Table 1) to show the relationship between copper thickness, resist thickness, and resolution capabilities of processes.⁵ Karl devoted many Tech Talks to “fine-line imaging” and to related topics such as photoresist adhesion, developing, fine-line etching, stripping, and pattern plating.

Semi-Additive Processes
The older mSAP processes used thinned copper, usually to nine or five microns, from half-ounce foil or very thin copper foil (usually with a peelable protection). They would usually have a flash copper strike and may use tin plating as the etch resist.

The IC substrates (for flip-chips) were always the leading edge of this technology, from 2005 onward, but quickly converted to the use of the Ajinomoto build-up film (ABF) from Japan that was additive electroless on the bare-etched, vacuum laminated dielectric films.

The advanced-modified SAP (amSAP) processes did away with the copper strike and further exploited the thin-copper foils.

Averatek’s new A-SAP^TM (or pure additive) starts with a treated copper foil on the laminate, but after drilling, the copper foil is etched away. This allows a new generation of nanoparticle Liquid-Metal Ink^TM catalysts to be used to prepare the surface for fine-grain electroless copper application. After pattern electroplating and resist stripping, this electroless copper, being only around 0.7 to 1.2 microns thick, permits a flash etch without any etch resist. These processes are seen in Figure 1.

With these new, improved catalysts and electroless copper products now available, Table 2 shows the newer capabilities of various SAP processes including the SAP and pattern plating for the ABF process used for flip-chip and other IC packaging substrates.

The trend is clear that organic (PCB) substrates are continuing to evolve down to less than five-micron trace/spaces. The most important characteristic is the surface smoothness and planarity of the dielectric. Figure 2 shows the reduction of trace/space as a function of device pitch and SAP process technology, as portrayed in the 2019 IEEE Heterogeneous Roadmap.⁶

Direct Metallizations
Considerable advances have been made in the direct metallization processes to replace electroless copper, introducing a simpler and less costly process for mSAP/amSAP. The proven direct metallization systems have added a new copper etch of 0.2–0.3 mm to eliminate carbon from the copper surfaces.

The simplified metallization process (compared to electroless copper) is shown in Table 3. While the direct metallization process is easier to control, it also has the advantage of one-third the space required and is environmentally friendly.

Heterogeneous Integration
The constant reduction in semiconductor transistor geometries have created a situation where it appears less costly to break up very large, complex dies into smaller dies and combine them with “modular” dies, now named “chiplets” and tiny discretes on an organic substrate using these exceedingly small traces and spaces along with very tiny vias as a “system-in-package”—now referred to as “heterogeneous Integration.” This can be seen in Figure 3.

The design trade-offs will be between trace geometry and its losses and innerlayers using ultra-HDI technologies. This is where the innovative technology of VeCS⁸ will provide vertical traces to any innerlayer using less space, easy plating and reduced electrical parasitics.

The increasing complexity of HIR will add more functionality to these substrates and result in modules, as seen in Figure 4, that will contain IC chips of various materials/connections, embedded components, RF/antennas, optical waveguides and even energy storage.

Conclusion
The prediction from YOLE Development about the future of packaging for these electronics out to 2030 is uncertain, as seen in Figure 5. There are overlapping capabilities currently down to 5/5-micron L/S and this will continue over time down to under 1/1 microns by 2030.

References

“Fine Lines in High Yield: Process and Material Adaptions for HDI,” by Karl Dietz, CircuiTree Magazine, December 2000.

“Fine Lines in High Yield: Circuitizing Requirements Driven by Packaging Designs,” by Karl Dietz, CircuiTree Magazine, February 2001.
“Fine Lines in High Yield: Semi-additive and Modified Semi-additive Processes for uBGAs and other Fine Line Interconnect Substrates,” by Karl Dietz, CircuiTree Magazine, December 2001.
“Fine Lines in High Yield: Fighting the Etch Factor and Etch Non-uniformity,” by Karl Dietz, CircuiTree Magazine, July 2002.
“Fine Lines in High Yield: Line and Space Resolution and Copper Etch Depth,” by Karl Dietz, The PCB Magazine, September 2010.
IEEE Heterogeneous Roadmap, by Paul Wesling, The Heterogeneous Integration Roadmap: Enabling Technology for Systems of the Future, SMT Pan Pacific Conference, Hawaii, January 2020.

Integrated Metallization System for High Density Interconnects and Modified Semi Additive Processing, Feng, K.; Spencer, T.; Watkowski, J., October 2013.
“Vertical Conductive Structures,” by Happy Holden, PCB007 Magazine, October 2021.
YOLE Development Report, Status of the Advanced Packaging Industry 2018.

Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard,?NanYa?Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and the author?of?Automation and Advanced Procedures in PCB Fabrication, and?24 Essential Skills for Engineers.?

This column originally appeared in the January 2022 issue of PCB007 Magazine.