Using Agile Analog’s Process-agnostic Analog IPs Can Help Solve Current Semiconductor Capacity Challenges

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The current Fab capacity challenges within the Semiconductor industry have resulted in ASIC and Fabless companies evaluating multiple foundries in order to meet chip production forecasts for the next several quarters. Agile Analog’s process agnostic Composa™ technology addresses the problem of portability of the analog IP cores that have traditionally required re-engineering to suit each different silicon process technology.

“This process specific re-spin each time a different foundry is used consumes valuable engineering effort that could be better focussed on value-added differentiating design work,” explained Barry Paterson, VP Product Marketing at Agile Analog. “When customers integrate our analog IP cores in their designs, we can automatically generate new versions of the IP using the PDK for a different process to enable access to capacity. 

The capability to enable access to any process technology also helps customers when moving to next generation of a product family that is typically on a smaller process node. The majority of enhancements usually occur in the digital implementation while the analog IP that provides foundation analog functionality, data conversion and power conversion typically remains constant. Maintaining the analog IP performance and features while having it regenerated by Agile Analog for a smaller process node allows customers to focus their valuable analog design engineers on innovative and differentiating design work rather than having to process port all analog circuits.