EIPC Summer Conference 2022: Day 1 ReviewJune 28, 2022 | Pete Starkey, I-Connect007
Estimated reading time: 18 minutes
EIPC board member Stig Källman, component engineer PCB at Ericsson Örebro, shared his vision and offered invaluable technical guidance and practical recommendation in his talk on setting the PCB trends and requirements for 6G PCB manufacturing.
He considers that making tomorrow’s designs with yesterday’s equipment, but capability matched, is the best way to create value and make profit. Emphasising the benefits of re-use and standardisation, his examples of standardised building blocks are Lego bricks and shipping containers. He recommends using cost-efficient layer stackups and via structures, avoiding over-design by understanding manufacturing variation, and achieving high manufacturing-panel utilisation.
He discussed PCB technology drivers: smaller lines, spaces and via sizes, high speed serial links, low-loss materials, high supply currents, optical waveguides in PCBs, and thermal management. He considered the impact of manufacturing on the environment, referencing energy efficiency, and the avoidance of hazardous substances.
Regarding laminates, he said, “Making a good soup we need the right recipes,” and regarding stackup options, he pleaded, “Don’t give us so many options! Teach us how to use the standard builds that are most produced with best tolerances to the lowest cost.” It was Ericsson´s ambition to phase out halogenated flame retardants in its products, with decisions made on a case-by-case basis, based on valid parameters, and the availability of environmentally sound alternatives.
To meet the challenges of current and future PCB technologies, Kallman’s laminate wish-list included low-Dk (less than 3) low-loss for high impedance, high-frequency RF, high-Dk (greater than 10) low-loss for low impedance, high-frequency RF, and magnetodielectric materials with a different balance between electric permittivity and magnetic permeability depending on the RF application. He sees it as important that the datasheets of halogen-free materials list their full mechanical properties, as well as data for the resin, including any fillers, covering the temperature range from -40°C to +220°C.
Discussing future material possibilities along the development path toward 6G, his view on resin development is that it should include three-way collaboration among the OEM, the material supplier, and the PCB supplier. He has a similar view on defining and measuring critical PCB design parameters that it should involve designer, manufacturer, and laminate supplier in equal proportions. And in new product introductions it is very important to ensure that the PCB shop has the opportunity to run production tests and be supported with manufacturing guidelines before any customer test boards were made.
Robrecht Belis, head of sales and PCB related business at Elsyca in Belgium, recommended a “shift-left” approach to the optimisation of bare board design, in order to identify and fix problems as early as possible in the development cycle.
As a specialist in the simulation of the PCB electroplating process, he discussed how multi-physics digital twin solutions could contribute to the optimisation of costs, product quality, time to market, and production capacity.
Quoting leading designer Rick Hartley, “Copper balancing should be done, not only at the panel level in PCB fab, but every PCB designer should be taught the many benefits of copper balancing and incorporate the concepts into their board designs.” Belis showed real examples of the significant variation in plating thickness of unbalanced designs and how thickness distribution can be optimised using proprietary software tools.
He cited testimonials confirming how the software has helped to identify critical areas at the design stage, to support engineers on the shop floor in predicting how different set-ups of designs and parameters influenced the outcome, and to accurately predict the plating parameters required to enable increased first-pass yields on new parts.
Stan Heltzel, materials engineer with the European Space Agency, described ESA’s approach to microvia reliability.
Describing PCBs as the nerves and veins of the spacecraft, he introduced the ESA web portal: European Space Components Information Exchange System, of which the PCB section (escies.org/pcb/) gives details of ESA Approved Manufacturers and Qualification Status of PCBs, ESA Qualification Status of PCB technology, ESA Approved PCB Manufacturers, ECSS standards for design of PCBs (ECSS-Q-ST-70-12C), and qualification and procurement of PCBs (ECSS-Q-ST-70-60C), as well as listing active ESA memos and checklists, historic ESA memos, and technology development and conference papers.
At the bottom of a long list of active ESA memos and checklists was ESA-TECMSP-TN-19672 Microvia Process Guidelines which gives a general process overview and specific process recommendations for laser drilling, pre-etch and cleaning, desmear, microetch, rinse, electroless copper and copper electroplating, as well as tests for qualification, lot conformance and in-process verification.
The document can also be used as a guideline for conducting a process audit. The guidelines have been drafted with support from PCB experts and experts from chemistry suppliers, and have been reviewed by the PCB manufacturers of the PCB/SMT working group.
Heltzel reviewed technology drivers: electrical performance, manufacturability, and reliability, with reliability depending on design, materials and processes, and manufacturability depending on capability and qualification. He demonstrated technology development with the example of the Apollo guidance computer of 1969 compared with a contemporary smart phone which was a million times more powerful, weighed a hundred times less and cost a thousand times less.
Introducing the HDI roadmap using a series of cross-section diagrams, he discussed the confidence interval of stress-strength analysis, failure life cycles, and microvia failure mechanisms. The approaches used by ESA to evaluate microvia designs were a review of the design with comparison to heritage and qualification, thermo-mechanical modelling, testing coupons and spare PCBs, and review of manufacturing processes. He described ESA’s procedures for Manufacturing Readiness Reviews for PCBs, which culminated in authorisation to proceed with manufacture, and discussed details of thermo-mechanical modelling, causes of strain on microvias, and microvia qualification and conformance testing.
There is work in progress using a standardised test panel in a round-robin campaign for high-reliability industry, which will provide a robust assessment of capability and reliability, secure the HDI supply chain, and validate several test methods.
It had been concluded that microvias can be used reliably, through review of design considering all critical features, and compared against a qualified envelope of technology features, with manufacturing processes optimised through mutual assessment among the supply chain. Compliance is demonstrated by test and inspection and qualification, loT conformance, in-process verification, and capability assessment.
“Stop resistance clouding your high-speed measurements,” said EIPC board member Martyn Gaudion, CEO of Polar Instruments, explaining why the distributed series resistance has to be removed from the measurement to make an accurate impedance measurement. He used 50 ohm coaxial cable to illustrate his point, different lengths of cable all having nominally the same impedance value. Impedance controlled PCB traces were, in effect, simulated coaxial cables in PCBs, so why were some PCB fabricators under the illusion that impedance changed with length? The reason was that, in fine line designs, DC resistance could cause inaccuracies in impedance measurement.
Gaudion illustrated graphically the effects of distributed series resistance and distributed shunt conductance. Distributed series resistance make the impedance appear to rise with length and it is necessary to remove its effect in order to achieve an accurate impedance measurement. Otherwise, it could be wrongly inferred that datasheet dielectric constants are incorrect.
To check whether series resistance was clouding the measurement, he suggested modelling the resistance and simulating the effect on a TDR trace by entering the trace geometry and the line length and seeing the expected result on the TDR waveform. In contrast, on broader line widths, the resistive effect could be safely ignored.
But if the DC resistance effect is ignored on fine-line traces, the TDR reading would be high compared with predictions. This could lead to concluding that the datasheet value for Er was incorrect, and might result in attempting to meet the impedance value with a revised geometry.
Polar is confident that laminate suppliers provide accurate measurements for Er and believe that de-embedding the DC resistance allows better correlation of results without artificially adjusting Er values. Page 2 of 3
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The SCHMID Group, a global solution provider for the high-tech electronics, photovoltaics, glass and energy systems industries, will be exhibiting at productronica in Munich from November 14 – 17, 2023.
The topic of intrinsic copper structure has been largely neglected in discussions regarding the PCB fabrication quality control process. At face value, this seems especially strange considering that copper has been the primary conductor in all wiring boards and substrates since they were first invented. IPC and other standards almost exclusively address copper thickness with some mild attention being paid to surface structure for signal loss-mitigation/coarse properties.
At PCB West, I sat down for an interview with John Andresakis, the director of business development for Quantic Ohmega. I asked John to update us on the company’s newest materials, trends in advanced materials, and the integration of Ticer Technologies, which Quantic acquired in 2021. As John explains, much of the excitement in materials focuses on laminates with lower and lower dielectric constants.
Printed circuit board (PCB) reliability testing is generally performed by exposing the board to various mechanical, electrical, and/or thermal stimuli delineated by IPC standards, and then evaluating any resulting failure modes. Thermal shock testing is one type of reliability test that involves repeatedly exposing the PCB test board to a 288°C pot of molten solder for a specific time (typically 10 seconds) and measuring the number of cycles it takes for a board’s copper layer to separate from the organic dielectric layer. If there is no delamination, fabricators can rest assured that the board will perform within expected temperature tolerances in the real world.