Siemens’ Calibre Platform Expands Early Design Verification Solutions

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Siemens Digital Industries Software announced a range of expanded electronic design automation (EDA) early design verification functionalities for its Calibre® platform for integrated circuit (IC) physical verification. Engineered to help IC design teams and companies get to tapeout faster, these new capabilities can help IC designers "shift left" their physical and circuit verification tasks by moving the identification, analysis, and resolution of complex IC and system-on-chip (SoC) physical verification issues into earlier stages of the design and verification flow.

Identification and resolution of issues earlier in the design cycle can not only help compress the overall verification cycle, but also provide more time and opportunity to improve final design quality. By providing tuned check support for these early-stage analysis, verification and optimization strategies using qualified signoff requirements, Siemens enables design companies to streamline their design processes, improve designer productivity and reduce time-to-market.

“Extending technology leadership in the EDA space requires constant improvement driven by a deep understanding of the specific challenges customers face in their daily work,” said Michael Buehler-Garcia, vice president of Product Management for Calibre Design Solutions, Siemens EDA. “The introduction of these new early design verification capabilities underscores Siemens‘ ongoing commitment to providing customers with the very latest technologies they need to quickly deliver world-class silicon products to market regardless as to the stage of the design they are working in.”

Among the new functionalities for the Calibre platform are:

• The Calibre RealTime Custom and Calibre RealTime Digital software tools, which provide in-design, signoff-quality Calibre DRC for custom, analog/mixed-signal, and digital designs. The Calibre RealTime interfaces provide direct calls to Calibre analysis engines running foundry-qualified signoff Calibre rule decks, helping to improve both design speed and quality of results by providing immediate feedback on design rule violations and recommended rule compliance. Calibre RealTime Digital now enables in-design fill with Calibre Yield Enhancer SmartFill, enabling designers to get foundry signoff fill from within their design cockpit, while Calibre RealTime Custom has added the ability to automatically track DRC across multiple regions to enable multiple edits to be fixed, tracked and checked simultaneously. 
• The Calibre nmDRC-Recon use model in Calibre RealTime Digital provides intelligent, automated analysis of immature and incomplete designs across blocks, macros, and full-chip layouts to methodically find and fix high-impact physical layout earlier in the design and verification flow. Extending the speed and designer debug gains already possible with the nmDRC-Recon use model, Siemens has now added the capability to flexibly “gray-box” out immature cells and blocks, yet still check DRC for interfaces to adjacent blocks or upper-level metal.  Gray boxing further accelerates performance and improves designer debug productivity by supressing nuisance DRC, resulting in up to 50 percent faster runtimes compared to nmDRC-Recon alone.
• Calibre nmLVS-Recon software provides intelligent, automated analysis of immature and incomplete designs for circuit verfication use models. With Calibre nmLVS-Recon software, a designer can efficiently perform short isolation (SI) to identify circuit errors. Short isolation mode in Calibre nmLVS-Recon does not require changes to design inputs or foundry rule decks, and executes only the short isolation step of Calibre nmLVS. This can speed up LVS execution by up to 30x, allowing designers to complete several iterations in a day whereas, previously, this might be an overnight execution.

The Calibre nmPlatform tool suite is also differentiated in the EDA industry with its integration across all major IC design and layout implementation tools. This seamless integration enables design teams to easily run Calibre tools at the intellectual property (IP), block/macro, and full-chip levels, all from their custom design or place and route (P&R) design cockpit. In addition, the Calibre plaform‘s unique viewing and debug capability can result in speed enhancements at all design stages.