AlixLabs to Be Granted First European Patent Relating to APS for Semiconductor Manufacturing
October 24, 2022 | PRNewswireEstimated reading time: 2 minutes

AlixLabs from Lund, Sweden, has developed a new, innovative method for manufacturing semiconductor components with a high degree of packing, eliminating several steps in the semiconductor manufacturing process - Atomic Layer Etch Pitch Splitting (APS)*. The method makes the components cheaper and less resource-intensive to manufacture and can open up a new path for a more sustainable mass production of electronic products. The method also makes it possible to manufacture tiny semiconductor components accurately and efficiently with manageable wafer fab equipment investments.
The company is now pleased to announce that the European Patent Office (EPO) has issued a notice of Intention to Grant their first European Patent. Europe is one of the most important markets for leading-edge semiconductor products due to the size of the EU inner market for electronic goods like smartphones, PC/laptops, tablets, automotive and internet servers, and hence crucial for AlixLabs to protect its innovative APS process here by IP.
In a statement from Dr. Dmitry Suyatin, CTO and Co-founder of AlixLabs on the origin of the invention and R&D activities in Lund, he said, "Our key technology is based on a surprising discovery that sidewalls act as a topographical mask in Atomic Layer Etch Processes. This technology has been proven for such different materials as Gallium Phosphide (GaP), Silicon (Si) and Tantalum Nitride (TaN) – all being critical materials to the semiconductor and optoelectronic industry. Besides already having secured a granted two US and one Taiwan patent, we are now delighted to announce that our European patent will also be granted and that we have more patent applications in the pipeline. A process of validating the patent in key countries in Europe is in process."
Dr. Jonas Sundqvist, CEO and Co-founder said, "The APS method is complementary for single exposure Immersion and Extreme UV (EUV) Lithography and corresponding multiple patterning technologies like self-aligned double and quadruple patterning (SADP resp. SAQP) as well as multiple exposure lithography-etch and directed self-assembly (DSA). However, APS can reduce complexity, capital expenditure and the environmental foot print for wafer manufacturing considerably. Besides that EU is one of the biggest markets for semiconductor components, the recent announcements of 300 mm wafer fab expansions and leading automotive sector means that it is more important than ever to have European IP".
AlixLabs: Dr. Dmitry Suyatin, Dr. Amin Karimi and Dr. Reza Jafari Jam discussing 300 mm wafer strategies in the Lund Nanolab cleanroom.
* Atomic Layer Etch Pitch Splitting (APS). As previously reported (April 30, 2021), The US Patent Office has approved AlixLabs's patent application for nanofabrication by ALE Pitch Splitting (APS). The US Patent Office has issued a patent (US10930515) on February 23, 2021 and recently the second patent (US11424130) on August 23, 2022. The patents covers methods to split nanostructures in half by a single process step using Atomic Layer Etching (ALE). The method can have a significant impact on the semiconductor industry by enabling sustainable scaling of electronic components and shrink chip designs further in a cost-effective way. The method is complementary for single exposure Immersion and Extreme UV (EUV) Lithography and corresponding multiple patterning technologies like self-aligned double and quadruple patterning (SADP resp. SAQP) as well as multiple exposure lithography-etch and directed self-assembly (DSA).
Suggested Items
July 2025 PCB007 Magazine: Sales—From Pitch to PO
07/18/2025 |Though all parts of a company are essential for holistic success, it is a foundational truth that a company lives and dies by its sales. If there are no sales, the company eventually ceases to exist, or as Henry Ford says, “Nothing happens until someone sells something.” In the July issue of PCB007 Magazine, we break down the sales stack and provide a guide to up your sales game.
Tightening of LPDDR4X Supply Drives Up Prices; Smartphone Brands to Accelerate Adoption of LPDDR5X
07/17/2025 | TrendForceTrendForce’s latest investigations reveal that major Korean and U.S. memory suppliers are expected to significantly reduce or even cease production of LPDDR4X in 2025 and 2026.
Beyond Design: Refining Design Constraints
07/17/2025 | Barry Olney -- Column: Beyond DesignBefore starting any project, it is crucial to develop a thorough plan that encompasses all essential requirements. This ensures that the final product not only aligns with the design concept but is also manufacturable, reliable, and meets performance expectations. High-speed PCB design requires us to not only push technological boundaries but also consider various factors related to higher frequencies, faster transition times, and increased bandwidths during the design process.
Knocking Down the Bone Pile: Addressing End-of-life Component Solderability Issues, Part 4
07/16/2025 | Nash Bell -- Column: Knocking Down the Bone PileIn 1983, the Department of Defense identified that over 40% of military electronic system failures in the field were electrical, with approximately 50% attributed to poor solder connections. Investigations revealed that plated finishes, typically nickel or tin, were porous and non-intermetallic.
Digital Twin Concept in Copper Electroplating Process Performance
07/11/2025 | Aga Franczak, Robrecht Belis, Elsyca N.V.PCB manufacturing involves transforming a design into a physical board while meeting specific requirements. Understanding these design specifications is crucial, as they directly impact the PCB's fabrication process, performance, and yield rate. One key design specification is copper thieving—the addition of “dummy” pads across the surface that are plated along with the features designed on the outer layers. The purpose of the process is to provide a uniform distribution of copper across the outer layers to make the plating current density and plating in the holes more uniform.