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ZESTRON to Present on Defluxing Ultra-Fine Pitch Die on CoWs at IPC APEX 2023
December 21, 2022 | ZESTRONEstimated reading time: Less than a minute

ZESTRON, a leading global provider of high-precision cleaning products, services, and training solutions in the electronics manufacturing and semiconductor industries, is pleased to announce that ZESTRON’s Senior Application Engineer, Ravi Parthasarathy will be presenting, “Process Considerations for Defluxing Ultra-Fine Pitch Die on CoWs”, at IPC APEX 2023 taking place in San Diego, California.
CoW (Chip on Wafer) is the next generation of CoS (Chip on Substrate) that first combines the chips to the interposer, adds wafer-level molding, and finally, they are connected to the flip chip (FC) substrate. This technology makes a better physical structure for accommodating very large die and larger overall interposer dimensions.
A continuation from the technical paper presented at APEX 2022 and titled “Defluxing of Copper Pillar Bumped Flip Chips,” this new study concentrates on cleaning under the next level of ultra-fine pitch CoW devices down to less than 25?m bump pitch and bump counts of more than 150K. This study focuses on the impact of wash temperatures and conveyor belt speed utilizing analytical/functional testing, including Visual Inspection, FTIR with color mapping, and SEM/EDX to assess cleanliness.
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ICT Spring Seminar: Nickel Not Welcome Here
03/12/2025 | Pete Starkey, I-Connect007After a miserable, dull, and damp English winter, a really pleasant nearly spring day with the sun shining and daffodils in bloom greeted delegates to the Institute of Circuit Technology Spring Seminar at Puckrup Hall near Tewkesbury, March 5, in Gloucestershire, UK.
Multicircuits Expands Capabilities with State-of-the-Art Automated Copper Via Fill Process
03/10/2025 | MulticircuitsMike Thiel, president of Multicircuits, a leading provider of high-reliability printed circuit boards, has announced the addition of a state-of-the-art automated copper via fill process to their advanced manufacturing capabilities. This strategic investment enhances the company’s ability to deliver cutting-edge solutions for demanding industries, including aerospace, defense, medical, and high-speed telecommunications.
EIPC 2025 Winter Conference, Day 2: A Roadmap to Material Selection
02/20/2025 | Pete Starkey, I-Connect007The EIPC 2025 Winter Conference, Feb. 4-5, in Luxembourg City, featured keynotes and two days of conference proceedings. The keynote session and first-day conference proceedings are reported separately. Here is my review of the second day’s conference proceedings. Delegates dutifully assembled bright and early, well-rested and eager to participate in the second day’s proceedings of the EIPC Winter Conference in Luxembourg.
Designers Notebook: Addressing Future Challenges for Designers
02/06/2025 | Vern Solberg -- Column: Designer's NotebookThe printed circuit board is and will probably continue to be the base platform for most electronics. With the proliferation of new generations of high I/O, fine-pitch surface mount semiconductor package variations, circuit interconnect is an insignificant factor. Circuit board designers continually face challenges such as component quantity and complexity, limited surface area, and meeting the circuit board’s cost target. The printed circuit design engineer’s prominent position demands the development of efficiently manufacturable products that perform without compromise.
DesignCon 2025, Day 2: It’s All About AI
01/30/2025 | Marcy LaRont, I-Connect007It’s hard to get away from the topic of artificial intelligence, but why would you? It’s everywhere and in everything, and my time attending presentations about AI at DesignCon 2025 was well worth it. The conference’s agenda featured engaging presentations and discussions focused on the technological advancements in AI, big data centers, and memory innovations, emphasizing the critical relationship between processors and circuit boards.