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Happy’s Tech Talk
By Happy Holden
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Happy's Tech Talk #21: Embedded (Flush) Circuits
In his Tech Talk series, Karl Dietz wrote several times about embedded circuits1, particularly detailing flush circuit technology and recessed circuit processes. In his column, Karl outlined two processes that have been used to produce these “flush” circuits:
1. Imprint technology, based on the work of George Gregoire at Dimensional Imprint Technology, Inc.
2. Circuit transfer process, based on Samsung Electro-Mechanics. The transfer process, using polished stainless steel as a conductive carrier, is not new. I was introduced to this plated-post process in 1971, when PACTEL in Westlake Village, California, demonstrated its 50-micron microvias, produced using photoresist and the plated-post transfer process. But as laser technology improved for microvia blind drilling, new applications were developed by Amkor and Siemens for using these lasers to create trenches for circuits and SMT lands.
The flush/embedded circuit (Figure 1) is compared to the conventional subtractive-etched PCB circuit. It has several advantages as the geometries shrink to under 75 microns:
- Reliability and performance are advanced as adhesion is from three sides.
- In many cases, solder mask is not required because lead-free solder paste will not flow or bridge tight geometries.
- Signal integrity improves at very high speeds.
- For some fab processes, photolithography is eliminated (organo-metallic solder pastes).
- An increased number of insulation materials can now be employed.
As seen in Figure 2, the embedded traces do not interfere with components assembled over them.
The transfer process starts with a polished metal substrate that has been coated with a thin conductive release agent. Next, the carrier is coated with a photoresist and exposed to UV light through a mask (or DD imaging) to define the circuit. Once the photoresist is developed, the carrier is cleaned, and metals are plated into the exposed image. Since the carrier will be removed later, the first metal plated (usually gold or silver) will be exposed after fabrication, followed by a plated barrier metal of nickel, and finally copper for conductivity. Following plating, a planarization step provides a flat surface for attachment to a permanent dielectric; then the steps are repeated until the entire circuit is connected. This process is shown in Figure 3.
The Laser Scribing Process
As I described earlier, laser drilling is an integral part of HDI fabrication. Several OEMs have developed processes that use the laser to scribe the traces and pads into the surface material (Figure 4). After metallization of the substrate and specialized electroplating2 (damascene fill), the metallization is flash-etched off, resulting in flush circuitry (Figure 5).
Electrolytic Copper Filling Processes
Filling an embedded trench but not the surface requires the new generation of copper plating chemistry.
Vertical and Horizontal Methodologies
One of the new critical process steps which must be mastered in this process is electrochemical deposition (ECD) or electroplating of the trench. Some of the key process specifications, which were transferred from plating wafers to plating panels, include deposition uniformity, substrate throughput, and flexibility for depositing multiple metal layers. Bulk plating, which is used in traditional PCB manufacturing, is not well suited to meeting these specifications.
A new panel-plating tool (racking) was designed to address the needs of advanced packaging on a panel substrate. In place of bulk processing, the tool was designed with a compact series of cells which process a single panel at a time. Using a vertical orientation in the plating cell allows high throughput in a small footprint and enables the inclusion of a set of features which are required for advanced packaging plating applications. The large number of cells and an optimized overhead transport system allow flexible processing with different metals, and a throughput of up to 60 panels per hour. The panels are gripped in a rigid holder during transport and processing, minimizing any issues arising from panel warpage.
Getting to a perfect copper surface required more than just replacing soluble anodes with IrO anodes. It required: 3
- New membrane technology to isolate the insoluble anode
- Testing and implementing advanced equipment designs
- Understanding the root causes for defects
- Understanding the impact of basic cell design
Shear Plate Agitation
Deposition of metal from a bulk solution involves the transport of metal ions across a hydrodynamic boundary layer at the active surface4. The effective thickness and uniformity of this boundary layer is a critical factor in the deposition rate and the quality of the deposit. The vertical cell architecture of the panel plating tool allows the direct application of shear plate agitation used in wafer plating tools. This style of agitation uses a reciprocating grating near the panel to generate turbulence at the surface and maximize transport efficiency of metal ions and other critical reactants5.
When the part to be plated includes deep or high aspect ratio features, it is possible for air bubbles to become trapped in the vias or trenches when it is inserted into the plating bath4. These air bubbles, held in place by surface tension, can delay or even prevent plating from occurring in those features by preventing the plating solution from making contact with the active surface. The most effective method for eliminating air bubbles is to bring the part under vacuum, and fill the chamber with degassed, deionized water. With no air present, the water fills all the recesses, and now surface tension acts to exclude air as the part is transported to the plating cell5.
Many OEMs, PCB fabricators, and OSATs have proposed and created prototype flush circuit ultra-HDI substrates, including Siemens, Samsung, WUS, Unimicron, and Amkor (Figure 6).
Further examples are supplied by WUS in Taiwan6. Figures 7 and 8 show the traditional mSAP subtractive process compared to the flush process of 1 ounce or half-ounce Cu foil on outer layers or inner layers. Many times, based on density, the flush circuits do not require solder mask to prevent bridging.
As illustrated in Figure 8, the design potential by WUS for RF and high-speed digital circuitry application are apparent in that:
1. There is improved reliability.
- Stronger foil-to-dielectric adhesion
- BGA ball adhesion to copper pad
2. Improved signal integrity (PIM)Trace near-rectangular geometry
- Smooth copper surface
- Minimize crosstalk
3. Other application possibilities.
- Selective copper thickness for power or heat dissipation purpose
- Very high-resolution outer layer circuit density using conventional chemistry (2.0-3.0 mil or 50-75 µm trace W/S
- Same net over two types of materials (patch antenna)6
- Karl Dietz devoted two columns (#125 and #184) to flush circuit technology, but only one went into details about recessed circuit processes (TT#184), The PCB Magazine, May 2011.
- “Selective Copper Metallization for Advanced Packaging,” by Rashid Mavliev and Robert Rhoades, Proceedings of the International Wafer-Level Packaging Conference 2020, San Diego, Calif.
- “Unveiling the Next Generation in Substrate Technology,” by Ron Huemoeller and Sukianto Rusli, IEEE ECTC, January 2008.
- “Innovative Panel Plating for Heterogeneous Integration” by R. Boulanger, J. Hander, R. Moon, R. Hollman, SMTA International, Minneapolis, November 2019.
- These techniques are illustrated in Happy’s Tech Talk #19: “Next-generation Electroplating Systems,” PCB007 Magazine, May 2023.
- This is from a conversation with WUS Vice President Joe Dickson, 2022.
Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and the author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers.
This column originally appeared in the July 2023 issue of PCB007 Magazine.
More Columns from Happy’s Tech TalkHappy’s Tech Talk #23: Large Panel Processing
Happy’s Tech Talk #22: Computer-aided Bare Board Testing, Revisited
Happy’s Tech Talk #20: Teaching Coding to Kids—The UK’s Micro:bit Tool
Happy’s Tech Talk #19: Next-generation Electroplating Systems
Happy’s Tech Talk #18: Putt’s Law and the Successful Technocrat
Happy’s Tech Talk #17: Can You Build EVs Like PCs?
Happy’s Tech Talk #16: Protocols for a Smart Factory Future
Happy’s Tech Talk #15: Printed Electronics Using Flex