Estimated reading time: 17 minutes

Happy’s Tech Talk #22: Computer-aided Bare Board Testing, Revisited

Error Correlation
The concept of a communication link between a test system and an external or "host" computer has been a key to the developments at HP’s SPCF. In response to the question of how often each of these errors are occurring, SPCF developed a computer program that ran in a microcomputer which was interfaced to their first test system. When the test system detected an error in a board being tested, it would tell the microcomputer about it. The microcomputer would log it into memory, and on request, correlate all the logged errors and produce a display with the number of times each error was seen, from the most frequent on down. The program would also count the number of boards tested and failed, and produce hard copy reports identifying the run, test results, and the most frequently correlating errors. A sample report is shown in Figure 5. This relatively simple tool has the following major effects:

1. It differentiates between "systematic" and "random" errors. Systematic refers to the same type of defect occurring repeatedly in the same location. Systematic defects are the foundation of process feedback.
2. It provides a constant diagnostic on the test system and fixture. By doing a correlation occasionally while testing, intermittent pins are soon highlighted, and a quick check of the failed boards confirms this.
3. It allows a drastic time savings when finding a good board. For example, highly correlating opens at the top of the display point to probable shorts in the board that was programmed too.

Test systems capable of logging and correlating detected errors are just now becoming available. Systematic errors most often point to artwork or design problems (i.e., close traces, narrowing line widths, scratches, dust, etc.). They also indicate tooling problems such as misregistration and drill skew. The nature of random errors indicates process problems such as whiskers and voids, but the assumption of random errors should be proven by statistical testing¹.

Phantom Errors
A phantom error is an electrical open/short which is reported by a test system but does not exist in the PCB being tested. Phantom errors are caused by the presence of solder mask, oxides, or etching residue in and around PCB holes, which act to insulate/short test probes from the holes.

At SPCF, software in the host computer allows ET operators to halt the test system when an open is detected, though electrical stimulus is still applied to the test points in question. By briefly reactivating the fixture in the test system, while observing status indicators, electrical contact to the PCB can usually be achieved. A key on the operator's terminal instructs the host computer to discard the error, and the test continues. Through detecting and discarding phantom errors during the test process, time is saved in troubleshooting and retesting. An estimated average of 15% of all errors reported in finished boards are phantom errors.

Testing in Panel Form
Testing in panel form refers to testing PCBs before they are routed out of the panel that contains them. A number of productivity advantages are realized in this way. Phantom errors are nearly alleviated because the boards have not yet been through a solder mask operation. Test throughput can be greatly increased by using multiple image fixtures oriented to the stepped and repeated PCB images in the panel. A number of boards are then tested at the same time as a single board. It is much easier to troubleshoot and repair boards before solder mask and graphics are applied. If a board cannot be repaired (i.e., due to inner layer shorts), it is scrapped before additional downstream costs are invested in it.

The geographical location of defects in a panel gives important clues to upstream causes. This information is lost when testing finished boards. Figure 6 illustrates the significance of geographical defects.

Currently available test systems will report errors in a panel as though it were a single finished board. A few setup parameters used by the SPCF computer allow it to indicate which image is failing, and it translates all errors back to the first image. A single image overlay (or roadmap) can then be used for troubleshooting. Error correlation displays indicate what images each error was seen in. Note: Each image in a multiple image fixture must be wired in the same connector-pin sequence. This has always been the normal wiring method used by SPCF fixture vendors.

SPCF System Overview
An overview of the current SPCF system may be helpful to those engaged in bare board test development, as stand-alone test systems having a number of the following capabilities will not be available in the near future.

The PCB test systems are located at SPCF, Building 71, in Sunnyvale, California. Each of the five test systems has an adjacent HP2621P terminal as an operator console. The test systems and terminals are linked to the electrical test HP1000 computer (one of five in SPCF). A test operator uses these terminals to initiate the test procedure by entering a workorder number (and possibly a part number if the boards have not been tested before).

The integral printer will document any defects as they occur, and these printouts can be attached to each printed circuit panel to allow the review of possible repair of the defect. Figure 7 shows a system diagram of the electrical testing and AOI.

The SPCF system described above has a number of major functions:

1. Translate test errors into various formats (absolute, x-y, etc.).
2. Correlate and store errors-by-run and run-to-run.
3. Download and save test programs to and from the test systems.
4. Store fixture and PCB descriptions.
5. Store run results by part number, workorder number, vendor, revision, and inner layer side number for a period of one year.
6. Generate various reports by time limit, part number, workorder, and vendor, detailing production information, worst offenders, graphical trends, etc.

Benefits
The major benefit of this new approach is that it focuses on preventing errors in the first place. It identifies systematic defects so their sources can be tracked down, it nearly eliminates phantom errors, and it provides information on random errors that can be used for process control. SPCF believes that the new system eventually will help them to achieve a zero-defect rate in electrical continuity for all boards made at SPCF.

So far, the most significant improvement has been seen in newly designed, complex multilayered boards. Systematic defects in these boards have been cut by nearly 30% since the system was fully implemented. More subtle systematic defects will be found as historical data accumulates and the more frequent defects are eliminated.

Another major area of benefit is vendor feedback. Some of the panels tested by SPCF are bought from outside vendors. SPCF can give these vendors precise data on the type, location, and extent of defects.

SPCF estimates that the new system has reduced repair labor costs by 30% because of reduced defects, fewer phantom errors, and prior knowledge of systematic defects. In addition, the system shortens test setup time by one hour per machine daily. Also, testing in panel form is several times faster than testing finished boards. Significant labor savings are seen in a number of other ways, because the system has practically eliminated paperwork that used to burden the operators, their supervisor, and process engineers. Figure 8 illustrates an operator in the process of testing a two-image panel.

Product cost analysis has been improved due to repair information and accurate test time information. Test costs can be predicted as well as machine throughput.

The test area and affiliated software was developed by test engineers from 1979 to 1981. The software was written and implemented in three phases to match test demands as well as available resources.

• Phase 1 was to develop error translation, error correlation, and a useful test results report. This was implemented on an IMSAI microcomputer in 8080 assembly language.
• Phase 2 was to interface all five machines to the HP1000 and generate in FORTRAN the control programs established as useful in Phase 1.
• Phase 3 was to define and generate an IMAGE-1000 database for the electrical test, troubleshooting, and repair areas. This phase included the control programs to supervise set up, download, and save of connection files, test, and test suspension, as well as routine QA, production reports and graphs.
• Phase 4 was to incorporate advanced statistical analysis (T-tests and F-tests) learned from the NIST Engineering Statistics Handbook and the free Dataplot software supplied by NIST¹.

Computer-aided Manufacturing^2–4

The electrical test/quality analysis system is one of five automation centers at SPCF. The other four centers control:

1. Chemical processes
2. N.C. fabrication
3. Manufacturing engineering
4. Manufacturing planning and control

This is a computer-aided manufacturing (CAM) strategy that has been implemented in most of Hewlett Packard's 44 manufacturing divisions throughout the world. The strategy follows a hierarchy of computer systems, each focused on specific requirements and functions. This hierarchy is summarized in Figure 10. Other papers on automation at HP’s PCB facilities are available in Automation and Advanced Procedures for PCB Fabrication5.

References

1. Handbook of Statistical Methods, and software, NIST/SEMATECH.
2. "A Distributed Approach to Computer-Aided Manufacturing,” by Happy Holden, Electronics Manufacturing Technologies and Systems Conference, February 1983.
3. "CAD/CAM in PCB Manufacturing,” by Happy Holden, Assembly Engineering, Page 40-43, July 1981.
4. "Computer Process Control in a PC Facility," by Happy Holden, 8th Annual Advanced Control Conference, September 1982.
5. Automation and Advanced Procedures in PCB Fabrication, by Happy Holden.

Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers.

This column originally appeared in the September 2023 issue of PCB007 Magazine.

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