Three Things to Improve High-Speed PCB Signoff, Part 2September 27, 2023 | Brad Griffin, Cadence Design Systems
Estimated reading time: 1 minute
Another challenge for SerDes is losses within the channel design. At high speeds, dielectric material can be very lossy, making the appropriate selection of the right material, length, etc., critical for the channel. Many questions about stackup, trace widths, and height from the ground plane need to be defined up front. Simulating a signal with a topology explorer tool extracted from the design can be used to set up and run sweep parameters and push min/max length/spacing values into the Allegro schematic constraint manager (system capture). The preliminary constraints and schematics flow is illustrated in Figure 1. As the design progresses with final decisions on stackup and material selections, these constraints can be adjusted.
With the schematics phase finished and the layout phase in progress, the next challenge is compliance with specifications. Specs are dependent on the technology—PCI Express (PCIe), USB, etc.—and, because each one has its own requirements, this can be a complicated process. During this analysis, it is important to make sure the correct transmitter and receiver IBIS-AMI models are being used.
For the channel, Cadence tools can be used to accurately model the channels and address specifications. This is done by using the board file created by the layout designer, selecting several or all the lanes (depending on how much time is available), and running either a 2.5D or full 3D analysis on the entire channel.
Using the results of the channel extraction, a compliance analysis can be run based on the desired protocol. Most likely this will not be a one-time event, as often some obscure requirement not identified in the preliminary phase will surface, requiring additional iterations.
To read the rest of this article, which appeared in the September 2023 issue of Design007 Magazine, click here.
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