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Happy’s Tech Talk #23: Large Panel Processing

Much of our current focus is on the U.S. CHIPS Act, and for the future of PCB fabrication and assembly, this is appropriate. I started my career in manufacturing thin-film RF (sapphire) substrates, as well as conventional multilayers and HDI. I have researched and built IC substrates for the past 50 years. I know we depend on the technologies that trickle down from semiconductor and RF substrates.

Panel size is an important aspect of PCB productivity, yields, and cost. If a fabricator or assembler can process larger panels, then their productivity increases and their cost per board drops—provided that yields are not affected. Yields are an important process parameter, as they affect all costs and performance measures; they are driven by defect density, and that affects considerations of larger panel sizing. Defect density is not often talked about in PCB fabrication, unlike wafer processing, where it is a driving factor.

The Poisson Model is used as the defect density model to predict yields in semiconductor fabrication. I use the reciprocal of this equation to calculate a PCB’s first pass yield:

FPY = 100/exp[(log CI/A)^B]1

Where: FPY = first-pass yield (%)

CI = PCB complexity index

A, B = Fabrication capability coefficients

When I started working in 1970, our IC and RF substrates were 100 mm in diameter (many were sapphire, as HP used silicon-on-sapphire, not pure silicon) and PCB panels were 12" x 12" (305 mm x 305 mm). Because of the popularity of our HP-35 scientific calculator, by 1972 we were making LED COB substrates on a new high-temperature laminate in 12" x 16" panels plated with nickel and silver (for thermocompression bonding). To reduce costs and improve productivity and capability, the panel size has constantly crept up to 21" x 26" (Figure 1). The new standard for IC substrate panels is 600 mm x 600 mm (Figure 1) and a production panel (Figure 2).

The semiconductor packaging industry’s move to a 600 mm square panel provides the ability to segment the 600-mm panels into four 300-mm square sub-panels for use with conventional 300-mm round wafer probe test equipment. This was a driving factor for the short term (Figure 2). Extending process capability for key lithography, metal deposition, and other processes to complete the 600-mm panel provided a challenging, yet achievable, target for equipment suppliers.

New Materials
The next generation of IC packaging is adapting to the demands of multi-die architectures. While silicon has supplied this requirement, its cost and characteristics are not ideal. Glass and improved organic materials have emerged to fill this need. This strategy is very consistent with the dramatic and emerging changes in electronic systems, such as in high-performance computing (HPC), AI, and a new era of self-driving and electric cars that potentially think and drive better than humans. This requires device, packaging, and computing architecture paradigms with an entirely different vision and strategy than transistor scaling alone. Packaging, which can be viewed broadly as system scaling, is now viewed as replacing Moore's law for enabling better devices and better systems (Figure 3).

Georgia Tech and its industry partners are developing a leading-edge glass packaging that is consistent with the needs in cost, performance, functionality, reliability, and miniaturization. In a technical article, they described the critical glass packaging technologies, and their R&D and commercialization status, as well as all the current and future applications. It compares glass packaging against other leading-edge technologies, such as Si and embedded packaging.

The requirement for the next-generation of substrate packaging must allow the shrinking geometries of interconnection and I/O pitch, lower dielectrics, and losses for the higher frequencies and suitability for the increased thermal heat dissipation required by all these devices. Glass is an ideal material, as it has been modified over the years to perform many different requirements. Figure 4 shows a close-up of 1 µm and 1.5 µm t/s in the organic ABF film on a glass panel.

As shown in Figure 5, typical Cu pillar flip-chip bonding has a die pad pitch of 100 µm with an I/O density of 105 I/O mm2. TSMC’s integrated fan-out (InFO) has a die pad pitch of 55 µm with an I/O density of 314 IO/mm2.[3] To further decrease interface pitch, new interconnect technologies were developed, such as Intel’s EMIB (embedded multi-die interconnect bridge), which can achieve a die pad pitch of 45 µm with an I/O density of 492 IO/mm2. The first-generation Deca M-Series, with a planarized structure above the encapsulated active die coupled with the patterning technology, achieved the same 45-µm interface pitch as compared to EMIB, without the need for complicated bridge chips embedded in substrates. With the new Gen 2 technology, this die pad pitch can be further scaled to 20 µm, thereby achieving a more than 5X increase in I/O density of 2518 IO/mm2. Gen 2’s advanced LDI and automatic optical inspection (AOI) equipment, combined with the patterning technology, provides a path for the ultra-high-density die pad pitch and RDL density required for chiplets and advanced heterogeneous integration. Through-glass-vias (TGV) and copper pillars are needed for interconnects and thermal heat spreading.

Summary

A 650 mm x 650 mm panel-level approach to fan-out (PLFO) technology is being utilized, which enables assembly of four 300-mm round or 300-mm square fan-out subpanels on a carrier panel. This technology enables the re-utilization of the reconstitution and die/package-level processing equipment, focusing the panel processing where the greatest cost benefit can be achieved in the redistribution layer process. The use of a carrier panel minimizes the warpage, permitting implementation of more RDLs without impacting processability. The flow is performed on the smaller form factor, minimizing die-shift considerations on the large panel. The same panel equipment and infrastructure can also be used for chip-last PLFO or high-density, high-quality coreless substrates. Process flow details will be shared based on a PLFO pilot line in use now. The new SEMI standard for large-panel arrays looks to lower the cost and improve performance and reliability for multi-arrays die substrates5.

Glass packaging is emerging as a next-generation packaging platform beyond organic and silicon packaging. It has been developed in both chip-first and chip-last 2.5D and 3D architectures. Georgia Tech and its industry partners have developed all the building block technologies necessary to manufacture.

References

1. HDI HANDBOOK, Chapter 3, by Happy Holden.
2. “Next Steps For Panel-Level Packaging,” by Mark Lapedus, Semiconductor Engineering, Dec. 20, 2021.
3. “Glass Panel Packaging as the Most Leading-edge Packaging: Technologies and Applications,” by Rao Tummala, Bartlet Deprospo, Shreya Dwarakanath, SMTA Pan Pacific Symposium, Hawaii, 2020.
4. “Large-panel fan-out perspective on cost, yield, and capability,” by Clifford Sandstrom and Robin Davis, Chip Scale Review, November 2022.
5. “A Hybrid PLP Technology Based on a 650mm X 650mm Platform,” by Eoin O’Toole, Semiconductor Engineering, July 25, 2023.

Further reading

“600MM Wafer-Level Fan Out on Panel Level Processing With 6-Sided Die Protection,” by Jacinta Aman Lim and YunMook Park, Proceedings of the International Wafer-Level Packaging Conference 2020, San Diego.

Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and the author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers. 

This column originally appeared in the October 2023 issue of PCB007 Magazine.