Avicena will Showcase the World’s Smallest 1Tbps Optical Transceiver at the SuperComputing Conference 2023 in Denver, CO

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Avicena, a privately held company headquartered in Sunnyvale, CA, is demonstrating the world’s smallest 1Tbps optical transceiver as part its LightBundleTM multi-Tbps chip-to-chip interconnect technology at the SuperComputing Conference (SC23) in Denver, CO. Avicena’s microLED-based LightBundle architecture supports unprecedented throughput, shoreline density and low power, unlocking the performance of processors, memory, and sensors.

Artificial intelligence (AI) is driving an unprecedented surge in demand for compute and memory performance, driven by applications like ChatGPT based on large language models (LLMs). These sophisticated models have an insatiable appetite for computing power and fast access to large amounts of memory, resulting in an urgent and growing demand for much higher density low-power interconnects between Graphics Processing Units (GPUs) and high-bandwidth memory (HBM) modules. Today, HBM modules must be co-packaged with GPUs because the GPU-memory electrical interconnect is limited to just a few millimeters in length. Subsequent HBM generations will require IC shoreline densities in the range of 10Tbps/mm or more. Conventional optical interconnects based on VCSELs or Silicon Photonics (SiPh) promise to extend the interconnect reach but struggle to meet size, bandwidth density, power, latency, operating temperature, and cost requirements. By contrast, Avicena’s microLED-based LightBundle interconnects provide higher bandwidth density, much smaller size, much lower power and latency, and very low costs.

“At Avicena we are excited to showcase the world’s most compact 1Tbps transceiver in the shape of a 3mm x 4mm CMOS ASIC using our patented microLED optical interface,” says Bardia Pezeshki, Founder and CEO of Avicena. “Everyone is talking about SiPh solutions for applications in AI clusters. However, for short reach interconnects with less than 10m reach, we believe that our LED based solution is inherently better suited because the compact size, higher bandwidth density, lower power and latency, and temperature tolerance up to 150°C.”

Avicena’s innovations are supported by key investors including Samsung Catalyst Fund, Cerberus Capital Management, Clear Ventures, and Micron Ventures.

“Optical interconnect technology has the potential to improve chip-to-chip and inter-rack performance,” says Marco Chisari, head of the Samsung Semiconductor Innovation Center. “With a roadmap to multi-Tbps capacity and sub-pJ/bit power efficiency, Avicena’s innovative LightBundle interconnects can enable the next era of AI innovation, paving the way for even more capable models and a wide range of AI applications that will shape the future.”