Estimated reading time: 12 minutes

Happy’s Tech Talk #24: Performance and Registration—Coupons to the Rescue

Registration is one of the most important features for any PCB fabricator, but the capability for multilayers is a lot of work on the fabricator’s part. CAM settings, multilayer lamination, X-ray analysis, AOI measurements, imaging capability, and drill accuracy all play an important part in this capability. Software and panel parametric coupons are important because they aid in registration performance.

Registration Software
Registration software (Figure 1) provides the database and files for artwork compensation for CAM tooling, as well as real-time compensation for multilayer shifting and drill variances.

Modern AOI, X-ray imaging, and IoT sensors, like confocal imaging, can be connected to registration software to provide real-time panel measurements to calculate the best modified drill placements for any inner-layer shifting and provide those changes to outer-layer direct imaging. This can improve yields while allowing for higher precision on controlled impedances (to ± 3%) as seen in Figure 2.

Other Performance Examples
Other registration performance examples (Figure 3) provide a recap of the system now in use at the world’s most modern Lean and green PCB fabricator, GreenSource Fabrication. The registration and performance software being used at GreenSource provides hindsight from production data, insight as to what’s happening in real-time, and foresight into improving the performance of WIP through prescriptive actions.

Parametric PCB Coupons
There are parametric coupons that can be placed on test panels or production panels that will provide data for registration software. There are currently five available and another three can be used as references and inspiration:

• IPC D-coupons
• CAT coupons
• IPC-PCQR² benchmarking panels
• HATSTM and HATS^{2 TM}
• IST coupons

For the DIY enthusiasts:

• IBM’s CITC coupon
• PerfecTest coupons
• HP’s PTS coupons

IPC D-Coupon
The IPC D-Coupons from IPC-2221B Appendix A are used for reliability testing of through-hole, and blind and buried vias from production panels. They are two sets of daisy-chain vias connected for monitoring resistance with the 4-wire Kelvin resistance measurements. Two Type-D coupons are shown in Figure 4g.

Conductor Analysis Test Coupons
Conductor analysis technology (CAT) is the longest running, commercially available parametric coupon system. Born out of an NCMS program with Sandia National Laboratory, founders Tim Estes and Ron Rhodes licensed the testing machine from Sandia and started CAT in 1994.The test equipment and methodology are patented under U.S. Patent No. 5,659,483. Because of the length of availability, its thoroughness, and the wealth of publications, the CAT coupons are the most used and benchmarked. Six coupons, all 25.4 mm x 25.4 mm (1.0" x 1.0") make up the primary sensors for CAT (Figure 4a-f). These are:

1. Conductor: Spacing
2. Via formation: Nets daisy chain
3. Registration: I/L and O/L
4. New registration: I/L and O/L
5. Solder mask registration
6. Impedance

The value of a parametric system such as CAT is its ability to capture the true capability of a process, procedure, machine, or materials. There are numerous features on each coupon such that they can be tailored to capture current capability. Complex as these are, they cannot be inspected or sorted, so they truly represent what is going on. For novice users, the temptation is to inspect them to get perfect samples. This usually proves to be a futile activity, as some features are, by design, beyond our current capability.

These coupons are all customizable by CAT:

• Conductor spacing (1 to 20 mils), via diameter, via land, daisy-chain sequence, number of layers, registration sensitivity and layers, via structure (through, blind, buried, skip vias, stacked, sequentially laminated, etc.)
• Impedance type (single-ended, differential, edge-coupled, broadside, coplanar, etc.)
• Overall thickness, as well as placement and panel size

Some coupons were designed to be removed and put in small testers4.

The primary equipment is shown in Figure 4g. This was designed by Sandia and consists of an alignment system, fixtures, and a bed-of-nails connected to a sensitive AC-chopped, 4-wire Kelvin resistance measurement system (Figure 4j) feeding a PC. In 1999, a portable system was designed so that readings could be made in production, using an Agilent 34401A voltmeter (Figures 4h and 4i). The portable system has additional coupons from 0.33" x 3.0" to 0.5" x 2.0" to facilitate placing on production panels, as well as software to automatically calculate responses. To improve the impedance measurements, the Polar RITS-510 robotic probe and measuring unit were added in 2003.

IPC-PCQR² Benchmarking Panels
Figure 4k shows a 14-layer via rigid PCQR² board illustrated by cross-section showing thickness ranges and various through-holes, blind, buried, subcomposite, and back drilled vias. In Figure 4l, various layers, panels, and structures are available under the IPC PCQR² program.

HATS and HATS^{2 TM}
Highly accelerated thermal shock (HATS) was developed in 2003 and HATS² technology was released in 2020 to add the capability to perform multiple cycle convection reflow simulation up to 260°C in accordance with IPC-TM-650 Method 2.6.27B, Method 2.6.7.2c, and other custom reflow profiles. This convection reflow simulation methodology with high speed in-situ resistance measurements can detect cracks and separations in the via structures that occur during the high heat/expansion of convection reflow which could reconnect mechanically at lower temperatures and not be detectable. HATS can test up to 72 of the IPC-2221B Type D coupons (Figure 5a-g) and 36 traditional HATS or single via HATS2 coupons for both multiple cycle convection oven reflow simulation and thermal shock/cycling between 55°C and 260°C (Figures 5c–g).

The seven nets in a HATS² are:

• Net 1: 36 via daisy chain of layer 1 and 2 microvia structures only (entire via structure is built on coupon but only microvia structure is measured)
• Nets 2 and 3: Single vias of layer 1 and 2 microvia structures only (entire via structure is built on coupon but only microvia structure is measured)
• Net 4: Entire via structure through the entire PCB including buried via is measured.
• Nets 5 and 6: Single vias of layer n/n-1 microvia structures only (entire via structure is built on coupon but only microvia structure is measured)
• Net 7: 36 via daisy chain of layer n/n-1 microvia structures only (entire via structure is built on coupon but only microvia structure is measured)

Interconnect Stress Test™ (IST)
IST is the oldest and now most used accelerated thermal via reliability system in the industry. Developed in 1989 by Digital Equipment of Canada, patented in 1994, and commercialized by PWB Interconnect Solutions in 1995, over 100 systems have been installed worldwide. Used by over 120 OEMs, EMS companies, and PCB fabricators, it has six licensed service centers around the world and is standardized by the IPC-TM-650 Test Method 2.6.26, the DC current-induced thermal cycling test.

A typical coupon is seen in Figure 6a. This is one that the OEM supplies for an IPC Class 3 board. This one has through-holes, blind microvias, and buried vias using a high-Tg, low-loss laminate. Two of these coupons are built with every board, and until an approved number of IST cycles are passed, it is not assembled. Failure means a return to the fabricator for analysis.

The IST method measures changes in resistance of vias and internal layer connections as the holes are subjected to thermal cycling. The thermal cycling is produced by the application of a high current through the resistive internal layer connections of a specific group of holes, usually 200 daisy-chained vias, interconnecting through two adjacent layers called the power circuit (Figure 6c). Switching the current on for three minutes creates heat to take the connections from room temperature to a designated higher temperature. Stopping the current and with forced-air cooling, the connections cool in two to three minutes (Figure 6f). Another group of interconnects, two independent daisy chains interconnecting 500 vias through any two inner layers at various levels, the ones under test, are the sense circuits (Figure 6b). An isometric view of the two sets of interconnects, running parallel to and sequentially overlapping, is seen in Figure 6d. The equipment providing the coupon fixturing, current, cooling and resistance measurement is seen in Figure 6e.

An accelerated failure will occur because of the differential thermal expansion of the interconnect structure. Failure can occur in several locations (Figure 6g), either a via crack, post separation, connection crack, or material delamination in a specific region within one or multiple areas. Cycling continues until the specific rejection criterion is achieved or the required numbers of cycles are passed.

IBM CITC/PerfecTest®/HP PTS Coupons
Plated through-hole reliability testing at IBM uses their current induced thermal cycle (CITC) PCB coupon. Covered as IPC-TM-650 2.6.26 Method B, this small, single net coupon of 100 vias is only 1.75" x 0.3" and designed by IBM to be used many times on a panel and easily adapted to in-line process monitoring. The test uses current to heat the coupon at 3 degrees per second to 245°C for a dwell time of 40 seconds and repeats the cycle for 200-700 cycles per day. The temperature coefficient of resistance (TCR) is measured continuously and used to determine the coupon’s temperature. A 4-wire resistance bridge monitors the via daisy chain. The coupon is shown in Figure 7.

The CITC cycles were verified by FEA modeling, TMA, and moiré and has been used by IBM for 30 years. The rapid nature of the test and the small size of the coupons has led IBM and I3 Corp., to be able to characterize many important steps in the PCB manufacturing process.

PerfecTest came along in 1989 to address the problems in multilayer material movement and drill registration. The coupons (Figure 7a, b) are placed at the outer edges of the multilayer panel. The coupons work by detecting which plated through-holes have detected the movement of a particular I/L copper wedge. Figure 7b illustrates the 0.002" increments from 1 to 9 mils in the X-Y axis that the coupon will detect. Coupons can be placed on every layer or just specific ones. Although no specific testing equipment is required, Figure 7c shows the PerfecTest unit equipped with analysis and data storage software.

PerfecTest closed in 2013 but many companies around the world continue to use the coupons.  A simple ET-continuity tester or home-built 4-wire Kelvin probe can be used to test panels after etching.

Hewlett-Packard’s PTS-parametric test system was created by its Printed Circuit Division in 1987 based on early HP coupons that had been used in production since 1972. It was designed after HP’s parametric dies that had been used in its wafer fabrication.  Those early coupons focused on inner layer shifting, by using the copper on I/L’s shorting to a plated through-hole, moiré patterns, and hole quality cross-sections. Additional influence came from a parametric printed circuit board used as a training and process vehicle for the first NanYa PCB facility in Taiwan, around 1983. This PCB had various design-rule technologies on it and provided feedback on how the process was improving.

The HP PTS was a group of seven coupons that could be placed on production panels or used on a parametric panel to provide a snapshot of the benchmarked capability of the process. The initial seven coupons (Figures 7a–f) were designed to test:

1. Outer layer registration
2. Inner layer registration and shifting
3. Conductors/pads open and shorts
4. Plated through-hole, I/L conductors continuity
5. Artwork defects
6. Solder mask registration
7. Etch factors

The coupons were all designed to be tested by a facility’s continuity testers using the bed-of-nails open/short testing machines. In this case, the tester was an ATG2000 grid tester. The tester’s fault-file was captured by an HP workstation and stored. Each coupon had a stored perfect response or netlist that was compared to the fault file, and the opens and shorts were translated to dimensional shifts or other parametric data. The RS/1 statistics program was used to produce control charts and statistical reports, as well as historic data.

This system can be seen in Figure 7a. Also seen in Figures 7b-c were the small stand-alone coupon testers that operators had to check the process immediately as a confidence indicator. These home-built milliohm meters worked with a simple one-ampere power brick, a four-digit digital panel meter and a machined-Plexiglas coupon holder with eight spring-loaded gold pins wired to a four-position rotary switch in a 4-wire Kelvin measurement scheme.   

The concept was adopted by Foxconn’s internal PCB fabrication group as a method of benchmarking its 16 large PCB facilities in China; the number of different coupons was extended to 24 coupons, many that, after measurements, are used for assembly performance benchmarking.

Summary
For as long as there has been printed circuit production, there have been coupons to test every factor. Many excellent coupons have been designed over the years, too many for me to address in this column. The choices now are greater than ever. Hopefully, you are using one of these systems. You can buy it, rent it, or develop it yourself. The economic pressures of competition and the impending deadline of new laws make that an imperative8. But without something, you will find it increasingly difficult to stay in business, either because of profitability or reliability.

References

1. XACT PCB Ltd./InGeniusX. 
2. XACT PCB Ltd. presentation, CPCA-2018, Shanghai, China.
3. 24 Essential Skills for Engineers, by Happy Holden. In addition, “It All Starts With Sensors,” SMT007 Magazine, August 2023; and “Happy’s DIY Solution to Chemical Control,” PCB007 Magazine, November 2020.
4. Conductor Analysis Technologies Inc.
5. “Highly Accelerated Thermal Shock Reliability Testing,” by Bob Neves, Rick Snyder, and Tim Estes, hats-tester.com.
6. “Accelerated Interconnect Stress Test for Total Interconnect Solutions using IST Technology,” by Bill Burch, PWB Interconnect Solutions, Feb. 5, 2004. 
7. “TECH NOTE: Test Resolution,” American Testing Corporation, Redmond, Wash.
8. “The Need For Statistical Tools,” by Happy Holden, CircuiTree, October 2002.

This column originally appeared in the November 2023 issue of PCB007 Magazine.