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Happy’s Tech Talk #26: Balancing the Density Equation

Printed circuit design and layout is a creative process that has profound implications for electronic products. With the need for more parts on an assembly, or the trend to make things smaller to be portable or for faster speeds, the design process is a challenging one. The process is one of “balancing the density equation” (Figure 1) with considerations for certain boundary conditions like electrical and thermal performance. Unfortunately, many designers do not realize that there is a mathematical process to the layout of a printed circuit. The density equation has two parts: the component wiring demand (Wd) on the left, and the substrate wiring capacity (Wc) on the right.

The four conditions are:

• Wd > Wc: There are not enough wires to complete the design
• Wd = Wc: Ideal, but nearly impossible to achieve in the time allotted
• Wd < Wc: About 20% is a good target to set, especially if autorouting
• Wd<< Wc: The normal situation where extra layers are used or tighter design rules than are required

1. Wiring demand > Substrate capacity: If the substrate capacity is not equal to the demand, the design can never be finished. There is not enough room for either traces or vias. To correct this, either the substrate has to be bigger, or components have to be removed.
2. Wiring demand = Substrate capacity: While optimum, there is no room for variability and to complete the design will take an unacceptable amount of time.
3. Wiring demand < Substrate capacity: This is the condition to shoot for. There should be enough extra capacity to complete the design on time and with only a minimum of overspecification and costs.
4. Wiring demand << Substrate capacity: This is the condition that usually prevails. By PC layout, the schedule is tight, and timing is all-important. Many choose tighter traces or extra layers to help shorten the layout time. The impact of this is to increase the manufacturing costs 15–50% higher than is necessary. This is sometimes called the “sandbag approach.” It is unfortunate since the models above would help to create a more planned environment.

Component Wiring Demand
Wiring demand is the total connection length required to connect all the parts in a circuit. When you specify an assembly size, then you create the wiring density in inches per square inch. Models early in the design planning process can estimate the wiring demand. Three cases can control the maximum wiring demand:

• The wiring required to break out from a component like a flip chip or chip scale package.
• The wiring created by two or more components tightly linked, say a CPU and cache or a DSP and its I/O control.
• The wiring demanded by all integrated circuits and discretes collectively.

There are models available to calculate the component wiring demand for all three cases. Since it is not always easy to know which case controls a design, I usually must calculate all three cases to see which one is the most demanding and thus controls the layout. The model I find most useful for Case 3 is Coors and Anderson’s “Statistical Wiring Requirement.”¹
The other widely used models are:

• D.P. Seraphim, R. Lasky, and C.Y. Li²
• H. Ohdaira, K. Yoshida, and K. Sassoka³
• W. Donath⁴
• S. Sutherland and D. Oestreicher⁵
• L. Moresco⁶

Coors and Anderson’s Density Model
In 1990, Drs. Paul Anderson, Grover Coors, and Lori Seward of the Colorado School of Mines proposed a statistical model for determining the total wiring requirements (Wd) for a modern digital PWB based on the stochastic model of wiring involving all terminals, their probability of length based on the distance of the second terminal (their probability distribution function), and the special geometry of the other terminals. By benchmarking existing successful PWB digital designs, the typical multilayer (Figure 3a) had the net length distributions seen in Figure 2a. This matches the probability distribution function (PDF) in mathematics, as seen in Figure 2b. Using a Gamma distribution function, the nets in the real board (Figure 2a) create the interconnect length histogram in Figure 3b. This model allows the calculation of the Manhattan Predicted Interconnect Density, δ.

Predicted Interconnected Density, δ

Substrate Capacity
Substrate capacity is the wiring length available to connect all the components. It is composed of three factors:

1. Design rules: The traces, spaces and via lands, keepouts, etc., that make up the geometries of the substrate.
2. Structure: The number of signal layers and the combination of through and buried vias that permit interconnection between layers and the complex blind, stacked, and variable depth vias available in HDI technologies.
3. Layout efficiency: The percentage of capacity from design rules and structure that a designer can deliver on the board.

These three factors determine how much wiring is available on the substrate to meet the wiring demand. The data is straightforward except for layout efficiency. Layout efficiency is a little used factor that expresses what percentage of wiring capacity can be used in the design. The equation for substrate capacity for each signal layer is below. The total substrate capacity is the sum of all the signal layers:

Wiring Demand Vs. Substrate Capacity
The key to meeting schedules and keeping manufacturing costs under control is layout performance metrics (substrate capacity/wiring demand). It’s an understanding of an optimum design and keeping track of how close you get to it. Practice balancing the design equation and doing what-ifs. Try achieving a layout performance of from 1.05 to 1.15. Typical layout efficiencies are shown in Table 1.
 

More examples of wiring models can be found in Chapter 19 of the Printed Circuits Handbook, Sixth Edition, or Chapter 16 of the Seventh Edition.
References

1. “A Statistical Approach to Wiring Requirements,” by G. Coors, P. Anderson, and L. Seward, Proceedings of International Electronics Packaging Society (IEPS), 1990, pp. 774–783.
2. Principles of Electronic Packaging, by D.P. Seraphim, R. Lasky, and C.Y. Li, McGraw-Hill, 1989, pp. 39–52.
3.  “New Polymeric Multilayer and Packaging,” by H. Ohdaira, K. Yoshida, and K. Sassoka, Proceedings of Printed Circuit World Conference V, Glasgow, Scotland, reprinted in Circuit World, Vol. 17, No. 12, January 1991.
4.  “Placement and Average Interconnection Lengths of Computer Logic,” by W. Donath, IEEE Transactions on Circuits and Systems, No. 4, 1979, pp. 272–277.
5.  “How Big Should a Printed Circuit Board Be?” by S. Sutherland and D. Oestreicher, IEEE Transactions on Computers, Vol. C-22, No. 5, May 1973, pp. 537–542.
6. “Electronic System Packaging: The Search for Manufacturing the Optimum in a Sea of Constraints,” by L.  Moresco, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 13, 1990, pp. 494–508.
    

Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and the author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers. 

This column originally appeared in the February 2024 issue of PCB007 Magazine.