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Advanced Electronics Packaging Digest

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Stay ahead of the technologies shaping the future of electronics with our latest newsletter, Advanced Electronics Packaging Digest. Get expert insights on advanced packaging, materials, and system-level innovation, delivered straight to your inbox.

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Asahi Kasei Develops Photosensitive Polyimide Film for Panel-Level Semiconductor Packaging

05/21/2026 | BUSINESS WIRE
Panel-level packaging has gained momentum in the semiconductor industry as manufacturers pursue higher efficiency and improved yield that can support next-generation packaging processes. In response to these market changes, Asahi Kasei, a diversified global company, has combined the features of its photosensitive polyimide (PSPI) and dry film photoresist (DFR) into a new photosensitive film.

Innovative Flash Copper Plating Technology

05/21/2026 | Andreas Schatz and Mustafa Özkök, MKS’ Atotech
The continuous push toward higher functionality, miniaturization, and performance in modern electronic devices—such as smartphones, wearables, and advanced computing platforms—has intensified the demand for high-density interconnect (HDI) printed circuit boards. Central to HDI performance is the reliable formation of blind microvias (BMVs), which serve as critical interlayer connections in modified semi-additive processes (mSAP).

Cadence Recognized as a Platinum Employer on the Where You Work Matters List

03/25/2026 | Cadence Design Systems
We're proud to be named a 2026 Platinum Employer on the Where You Work Matters List. This recognition reflects our commitment to building high-quality jobs and expanding opportunities for our workforce.

Connect the Dots: The Future of Designing for Reality—Pattern Plating

02/05/2026 | Matt Stevenson -- Column: Connect the Dots
Last month, I discussed the outer-layer imaging process and offered tips for designers to help ensure smooth manufacturing and high-quality output. The next step in the manufacturing process is copper pattern plating, where fabrication can be tricky, and design precision is even more important. The board is now ready to have the copper traces, through-holes, vias, pads, and other elements specified in the original CAD design plated to copper thickness requirements. I will identify some key design considerations for pattern plating, break down the process, and offer design tips for a successful outcome.

Elephantech Unveils HDI Microvia Formation Process Using Copper Nanoparticle Ink

12/29/2025 | Elephantech
Japanese deep-tech Elephantech announced successful development of an innovative process to form High-Density Interconnect (HDI) microvia leveraging the company’s copper nanoparticle ink, named “Cu Nano Direct Plating.”
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