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Happy’s Tech Talk #40: Factors in PTH Reliability—Hole Voids

When we consider via reliability, the major contributing factors are typically processing deviations. These can be subtle and not always visible. One particularly insightful column was by Mike Carano, “Causes of Plating Voids, Pre-electroless Copper,” where he outlined some of the possible causes of hole defects for both plated through-hole (PTH) and blind vias. Some of these causes are:

• Poor drilling resulting in rough hole walls (many possible causes)
• Non-optimized laser drilling for microvias (six different parameters to consider)
• Improper material curing

Other pre-metallization causes can be:

• The desmear operation that is not in control (the solvent conditioning, alkaline permanganate, neutralizer, and glass etch)
• Inadequate textured Cu surface for palladium coverage

These can contribute to minimum or insufficient metal coverage in the conductor via, resulting in partial voids that lead to premature hole failure. 

For further discussion on this important topic, I will reference the work of a dear friend and colleague, Dr. Karl H. Dietz, a renowned figure in the printed circuit board (PCB) industry who passed away in 2020. He had a long and influential career at DuPont, where he contributed significantly to the advancement of electronics materials and processes. He was widely recognized for his technical expertise and dedication to knowledge sharing, particularly through numerous technical publications, seminars, and training sessions.

For nearly two decades, he served as the technical editor of a primary industry publication, where his "Tech Talk" columns (the predecessor of my own) offered practical insights into PCB fabrication challenges, including the topic addressed in this article: via voids and failures. The following is an overview of several of Karl’s insights on via reliability.

Understanding Hole Voids in PCB Fabrication
Karl wrote that hole voids, also known as conductor via through-hole voids, are a category of defects in PCBs that occur due to insufficient or missing metal coverage inside the conductor via. These voids can significantly impact the electrical reliability and structural integrity of the circuit board. He stated that these deficiencies generally stem from two causes: inadequate metal deposition within the via or the subsequent loss of metal after initial deposition.

Inadequate metal deposition can result from faulty plating parameters such as incorrect bath chemistry, improper agitation, suboptimal current or current density distribution, or insufficient plating time. Additionally, metal deposition can be obstructed by physical interferences like gas bubbles, particulate contamination, or organic residues.

Conversely, metal loss can occur due to chemical etching or mechanical failures such as blow-holing, cracking, or flaking of metal deposits. Understanding the full range of causes requires a methodical approach to analyzing defect types, recognizing void patterns, and tracing issues back to their root causes.

IPC-based Defect Analysis Framework
Karl recommended following a systematic troubleshooting process akin to the IPC Troubleshooting Guide. This includes:

• Starting with a clear defect description
• Recognizing and categorizing the defect
• Understanding the cause-and-effect chain leading to void formation
• Walking through each processing step involved in via formation
• Identifying distinctive void patterns and locations to trace root causes

Drilling and Mechanical Considerations
Hole void formation can begin at the drilling stage. Key concerns include the strength of the bond between copper and resin. A particularly vulnerable area is the bond between the oxide bonder and the prepreg layer, which tends to be weaker than the bond between copper and the core dielectric. This can result in separation, often observed as a "pink ring."

Rough drilling, or rough drilling combined with pink ring conditions, can lead to defects such as wedge voids and blow holes. Wedge voids form at the bonder interface and may be concealed by electroplated copper. If moisture becomes trapped in these voids and later vaporizes during high-temperature processes like reflow, it can rupture the copper plating and create a blow hole.

Desmear and Etchback Processes
The desmear process (See Figure 1) is designed to remove resin smears from inner-layer copper using oxidative chemicals like permanganate. It usually follows a resin-swelling step and is succeeded by neutralization to remove residues. Glass fiber etchback typically employs hydrofluoric acid. Two significant issues can result from poor desmear: blow holes due to trapped liquids and hole wall pull-away caused by smear residue blocking copper-to-copper bonding.

Pre-electroless Catalysis Sequence
This multi-step chemical process is prone to various failure modes that can result in hole voids. Problems may stem from incompatibilities among the desmear, etchback, and electroless chemistries. Issues affecting palladium catalyst coverage include poor temperature control, improper catalyst concentration, and inadequate dwell time.

Voids on glass areas can result from insufficient or excessive etching, weak catalyzation, or a sluggish electroless bath. Voids on resin areas may be due to incomplete neutralization, plasma residues, poor conditioning, or inadequate catalysis.

Electroless Copper Metallization Defects
Gas bubbles, solid particles, or organic films can interfere with plating and catalyst deposition. Entrapped gas bubbles—either from external sources (e.g., air entering the bath) or internal sources (e.g., hydrogen evolution during the electroless process)—can create symmetrical voids near the hole center. These resemble plating pits, with sloped copper at the edges (See Figure 4).

Particles blocking plating may become embedded in surrounding copper. Their nature can be determined using techniques like EDX (for inorganic particles) or FTIR (for organics). Eliminating gas bubble voids involves using agitation techniques such as bump and vibration, along with optimized panel spacing and paddle stroke (See Figure 2).

Electroplating-related Voids
Acid copper plating baths generally produce fewer voids due to high efficiency, but improper practices like excessive current or ripple can lead to hydrogen evolution. Tin baths are less efficient and more prone to gas issues unless additives are used to suppress pitting.

Air bubbles trapped in holes during bath immersion are a common problem. Solutions include using angled plating racks, paddle agitation, and air sparging. However, air sparging itself can introduce gas. Supersaturation from filter pumps can form bubbles, as can flaws on hole walls. Eductors are increasingly favored as a better alternative.

Plating-related voids can arise from poor throwing power, poor current distribution, agitation faults, and filter or anode issues. Particulate contamination may indicate worn filters or damaged anode bags.

Rim Voids and Their Causes
Rim voids are metal coverage gaps near the surface of the board. Typically caused by photoresist entering the hole, they appear 50–75 microns from the board surface. The problem occurs when hot air in the hole during lamination cools, creating a pressure drop that pulls resist into the hole (See Figure 3).

Contributing factors include:

• Moisture in the hole prior to lamination
• Small-diameter or high-aspect-ratio holes
• Long intervals between lamination and development
• Changes in photoresist formulation or lamination technique
• Drying the board adequately after surface preparation is the most effective remedy.

Tenting Process Defects
In tent-and-etch processing, a punctured tent allows etchant to enter the via and dissolve copper. Since puncturing both tent sides is rare, copper tends to erode from one end, resulting in an asymmetrical void tapering toward the broken tent. In extreme cases, all copper may be removed.

Direct Metallization Process Voids
Direct metallization eliminates the traditional electroless step, using palladium, carbon/graphite, or conductive polymer coatings. Voids may result from insufficient catalyst or polymer deposition, particularly due to inadequate hole wall conditioning.

Brushing panels after carbon deposition can remove catalyst near hole rims, preventing plating continuity. Pumicing after deposition can dislodge particles. While graphite processes tolerate brushing better, both processes require careful handling.

Voids Due to Copper Removal
Even after successful copper deposition, copper can be lost due to:

• Moisture in holes leading to oxidation
• Aggressive microetching
• Blistering or flaking of deposits
• Excessive brushing during surface prep

"Ring voids" occur when copper is brushed off around the hole rim. These appear as crescent-shaped gaps, often matching the machine direction of brushing. An unusual defect is the "corner void," where copper is missing from all four via corners. This may be caused by thin deposits at high-current-density areas due to overuse of levelling agents. Reducing paddle agitation or leveller concentration can alleviate the issue.

Conclusion
Hole voids in PCBs can result from a wide array of process issues, starting from drilling and extending through plating. Each void's location and shape can provide critical clues about its origin. Since multiple interacting factors often contribute to void formation, a thorough, step-by-step process review is essential to identify and resolve these defects.

Resources

• “Tech Talks #114–#117,” by Dr. Karl Dietz, March-June 1995.
• “Desmear—The Key Processes for Reliable Through-plating of Printed Circuitry,” by A. Angstenberger, Circuit World, Vol. 20, No. 4, 1994.
• “Plated Through-hole Processing: An Integrated Approach,” by Mike Carano, Plating and Surface Finishing, August 1994.
• “Process Control of Electroless Plating,” by Mike Carano, Proceedings, FabCon, May 1994.
• “Through-Hole Coverage Keys,” by W. T. Eveleth et al., Circuits Manufacturing, December 1986.
• “Plating Blockout During Gold Electroplating of Hybrid Microwave Integrated Circuits,” by J. Reagan & O. Qutub, Plating and Surface Finishing, January 1991.
• “Reducing Plating Voids,” by M. Lefebvre, Printed Circuit Fabrication, Vol. 16, No. 4, April 1993.
• “The Chemistry of Plating Small Diameter Holes,” by J. J. D’Ambrisi et al., PC Fab, April 1989.
• “Preventing Resist Related Through-hole Voids,” by G. S. Cox & W. L. Wilson, Technical Bulletin TB-9527, DuPont Electronics.
• “Review of ‘Direct Plate’ Processes,” by Karl H. Dietz, AESF SUR/FIN ’95, Baltimore, June 1995.
• “Antipitting-Zusaetze fuer galvanische Electrolyte,” by V. Mirtschewa, Galvanotechnik, 1991.
• “Reducing Copper Plating Pits in PWBs,” by R. A. Olson, August 1991.
• “A Farewell to Pitting,” by M. Jani & P. Diehl, Printed Circuit Fabrication, Vol. 16, No. 3, March 1993.

Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and the author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers. To read past columns, click here.

This column originally appeared in the June 2025 issue of PCB007 Magazine.