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Happy’s Tech Talk #28: The Power Mesh Architecture for PCBs

A significant decrease in HDI substrate production cost can be achieved by reducing the number of substrate layers from conventional through-hole multilayers and microvia multilayers of eight, 10, 12 (and more), down to four. Besides reducing direct processing steps, yield will increase as defect producing operations are eliminated.

This Tech Talk describes the power mesh architecture (PMA), an innovative interconnection topology that leverages the production technologies of microvias, via-in-pads, and fine-line lithography to allow planar power distribution and dense signal interconnection on only four metal layers.

The PMA was derived from the Interconnected Mesh Power System (IMPS), developed and patented by the High-Density Electronics Center (HiDEC) of the University of Arkansas, Fayettville, Arkansas.  The IMPS topology was created to reduce the cost and metal layers on thin-film and ceramic multichip modules. Power distribution characteristics of IMPS are presented as measured from various test vehicles1.

In this column, the PMA for PCBs and impedance tables are presented. The initial application of PMA is shown, as well as an application that helps develop the wiring density model for PMA. Finally, the eight-step design process is outlined to create a PMA board.

An Introduction to the Benefits
In the mid-1990s, thin film multichip modules (MCM-D) were supposed to be the salvation of the interconnect industry. The fine-line lithography would allow miniaturization with ease. Unfortunately, the four or five metal layers to which integrated circuits were wire bonded proved to be too expensive when compared to printed circuit multilayers and the emerging silicon integration on ball grid arrays.

The test vehicle was built on 2-mil Sheldahl material, an adhesiveless polyimide film called ViaThin.  The basic design rules are 50 mm lines and spaces and 150 m via target lands over 25 m laser-drilled vias. The IMPS mesh consisted of 200 µm lines and 50 µm spaces, with the lines offset from the via row or column centers. Wire-bond pads consisted of 200 µm x 350 µm rectangles on both metal layers, tied together with two vias.

The test vehicle showed conclusively that the IMPS topology could be applied to MCM-Ls and BGA substrates without the use of multilayering.

Power Mesh Architecture
In 1993, a large electronics OEM had the problem of having to redesign the control board of its largest 3.5" hard disk drive. The boards were a standard 3.87" x 5.45", but the problem was that they wanted to cut a 2.8"-diameter hole in the board so that another platter could be added to the drive. This would enable the drive to have a capacity of 16 GB, quite a capacity for 1993. The solution to the loss of nearly 5.8 square inches out of 17.5 square inches was to employ microvias and microvia-in-pads. The new microvia board (called Lynx) was designed with a reduced surface area and as a six-layer design (1+4+1), two fewer layers than the original.

Reading about the IMPS topology from HiDEC in 1994, the Lynx board was again redesigned to a four-layer construction. To minimize the microvias, the outer two layers (1 and 4) were flooded with ground, and only power and signals were placed on the inner layers. Figure 1 shows the new power-signal routing architecture, which was called power mesh to differentiate it from IMPS.

Electrical Model
The original Lynx board was not a controlled impedance, but additional PCB designs were that used power mesh. The consensus is that power mesh is an offset coplanar stripline. Figure 2 shows this cross-section of the offset coplanar stripline. The table shows the values for 50-ohm single-ended and 100-ohm differential impedances for different trace widths, spacings, core thicknesses, and overall thicknesses.

The crosstalk model indicates that the PMA creates a naturally low crosstalk condition. Each signal trace of X width is approximately 3X or 4X distance from the next signal, depending on the power trace width. This creates horizontal crosstalk of less than 2%. The vertical crosstalk is extremely low. From 15 mV/V for thin cores (0.012") to 2.6 mV/V for a thick core (0.051").

PMA Application
The first PMA was completed in 1994. The Lynx multilayer is shown in Figure 3. The inner layer FR-4 core (Figure 3a) was 12 mils thick (0.012"). The initial design used epoxy-resin coated copper foil of about 2-mils thick as the microvia layers 1 and 4. The microvias were 7 mils in diameter with 14-mil pads. Traces and spaces were 5 mils.

Figure 3b shows the finished power mesh multilayer. Without any traces on the surface—as all components had via-in-pads—the unbroken ground plane serves as the effective ground return and impedance reference. It was also highly effective as an RFI/EMI shield. Switching noise was reduced because the ground connections were micro-resistance and had no inductive or capacitive elements in series to the ground connection. Similarly, noise budgets were improved because the connection to power had the minimum inductance and capacitance, nearly 1/10 that of a through-hole and trace connecting the component land.

Designing With PMA
The one discouraging characteristic of the PMA is that EDA tools do not recognize nor automatically design with the PMA. That does not mean you cannot design with PMA; it just means you must do it by hand. The process for designing a printed circuit with power mesh can be simplified to eight steps:

1. Build a special library for all fine and extra fine pitch geometries that include locations for blind via-in-pads.
2. Create the board stackup in the EDA tool for a four-layer or six-layer PMA.
3. Place all parts at a closer proximity. The critical factor in placing parts is to place the power pins and connections on a grid approximately equal to the power mesh traces’ center-to-center distance.
4. Break through all signal and power nets using blind vias-in-SMT pads.
5. Protect all breakthrough vias so that they are not moveable.
6. Route the power traces to all power pins and connections and protect them. Route critical timing and clock lines and protect them, then route the remaining signal nets on one inner layer and only orthogonal routings on the other inner layer. Buried vias are used to transition from one layer to the other.
7. Complete the power mesh traces to fill in missing legs and balance the power mesh over the entire board’s surface. Blind vias need to be placed at each intersection of the same power levels (Vcc or Vdd) so that a power mesh results on the two layers that provide current distribution uniformly across the board. Clean up the board to minimize vias and trace length. Diagonal routing is okay now that routing is complete.
8. Expand all power traces (the mesh) until they meet a signal trace or another voltage level trace. This will create the maximum surface area for the power mesh traces and increase the distributed capacitance between power and ground. Fill the outer layers with ground plane and then stitch the ground planes together where possible (Figure 4).

Wiring Model

In 1994, StorageTek, an OEM in Colorado, conducted performance benchmarking with microvia designs and fabrication². The successes of that program contributed to its continued use of microvias. In 1998, it became apparent that they required some wiring model to indicate that a microvia structure was required. In performing that model development, a power mesh benchmark was designed for one of the microvia boards³. Figure 5 shows the two inner layers of the four-layer power mesh structure and two of the six inner layers from the original eight-layer through-hole design. The wiring density model for the PMA is:

Power Mesh = 17 to 40 signal inches per square inch per layer (dependent on trace width and spacings)

• Calculate the Statistical Wiring density using Coors, Anderson & Seward⁴
• Calculate the Manhattan Wiring Density using Wd=0.0068(X)^2 – 0.1644(X) + 35.1, where X is the Coors Statistical Wiring Density
• Calculate the Routability Index for Power Mesh³
• Calculate the Layout Efficiency using: L.E.(%)= 4.0642(RI)^-1.189, where RI is the Routability Index

Figure 5: Power mesh example at StorageTek provided coefficients for density models: a) The two PMA inner layers compared to b) two of the six inner layers of the original eight-layer TH design; c) circuit side view and cross-section view of the finished power mesh board.

Summary
The microvia topologies of power mesh have demonstrated the application to simplifying complex multilayer, PBGAs, and MCMs. IMPS can reduce the structure to a two-metal interconnect, while power mesh uses a four-layer reinforced laminate structure. These results show that these topologies have the capacity of positively impacting how electronic products are packaged and Interconnected.

References

1. Happy’s Tech Talk #27: Integrated Mesh Power System (IMPS) for PCBs, by Happy Holden, PCB007 Magazine, March 2024.
2. “A Comparison of Through Hole and Microvias in Printed Circuit Design,” by R. Charbonneau, The Board Authority—HDI, Vol.1, No.2, June 1999, pp. 88-94.
3. “Predicting HDI Design Density,” by Happy Holden and R. Charbonneau, The Board Authority-HDI (I), Vol.2, No.1, April 2000, pp. 28-31.
4. "A Statistical Approach to Wiring Requirements," by G. Coors, P. Anderson, and L. Seward. Proceedings of the IEPS, 1990, pp. 774-783.

Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and the author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers.

This column originally appeared in the April 2024 issue of PCB007 Magazine.