It’s Only Common Sense: Create Passion That Customers Feel
Punching Out: How to Stay Focused in Business and M&A
Siemens Digital Industries Software announced the Innexis product suite, a complement to its industry leading Veloce™ hardware-assisted verification and validation system.
Building on the success and rapid adoption of Veloce, Siemens’ Innexis product suite delivers a set of capabilities to address customer demand for shift-left software in the early phases of IC development. These products include a hardware/software development flow from virtual to hybrid to full RTL, an architecture native virtual platform for early high-speed software development and a simulation backplane that enables the development of digital twins in Siemens’ PAVE360™ software for software-defined vehicles and other complex systems.
“The complexity of integrated circuits (IC) is increasing exponentially, designers need more efficient methodologies to meet industry demands. Veloce has seen rapid adoption by industry leaders to help solve this critical bottleneck. The Innexis product suite extends workflow improvements from Veloce to help our customers shift left their IC development and debug cycle,” said Jean-Marie Brunet, vice president and general manager, Hardware-Assisted Verification, Siemens Digital Industries Software. “This enables IC design to begin months before final RTL, all while using a common software workload across the development process.”
Adoption of a shift-left approach for software development and IP verification processes is now mandatory. As chip designs become increasingly complex due to more demanding software workloads, it is critical to enable the development and execution of realistic workloads early in the design phase. A proactive shift-left software approach helps mitigate the risk of identifying issues late in the development cycle.
“The implementation of Innexis in our development process has significantly enhanced software and system validation performance, thereby improving the efficiency of our teams and projects. By enabling heterogeneous component modeling within virtual platforms, it allows us to create realistic high-speed models of System on Chips (SoCs),” said Ari Hautala, Principal System Architect, Nokia Mobile Networks. “Furthermore, the integration of these high-speed virtual platforms with RTL IP on Veloce emulators facilitates superior overall performance while still permitting precise cycle-accurate performance and power analysis on RTL model components. Additionally, Innexis offers exceptional visibility and debuggability for the SoC design, along with the capability to integrate and execute a large number of complex test cases effectively.”
Currently, the Innexis product suite consists of:
Innexis Developer Pro: Innexis Developer Pro software provides a connected development flow from virtual to hybrid to full RTL. This provides a comprehensive environment for accelerating the creation of complex SoC design supporting a wide range of use-cases including seamless hardware-software co-development, co-validation, and pre-silicon cycle accurate analysis and validation. Innexis Developer Pro supports the modelling of complex SoC’s with heterogeneous cores and custom SystemC model components. In addition, it provides the ability to run in both virtual plus RTL hybrid mode for high performance execution, and then at a time of interest switch to full RTL emulation enabling high accuracy analysis of the full SoC when required.
Innexis Architecture Native Acceleration (ANA): Innexis Architecture Native Acceleration software is a cloud- based high-speed virtual platform. By running natively on Arm based servers the software workloads run at much higher speeds than on typical instruction set simulation based virtual platforms. Cloud hosting also provides scalable compute resources and simple browser-based access and tools. Innexis Architecture Native Acceleration can also run on local Arm based servers if preferred. In both cases it enables early software development and testing, and early software defect identification.
