Alphawave Semi Delivers Foundational AI Platform IP for Scale-Up and Scale-Out Networks

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Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world’s technology infrastructure, bolsters its leadership in foundational AI silicon connectivity subsystems through silicon proven chiplets and IP subsystems on advanced process nodes and package types. This is set to be showcased at the TSMC 2025 North America Technology Symposium.

Scaling connectivity efficiently and effectively to support the growth of AI clusters requires high-speed, low-latency interconnects to handle the massive data throughput required by AI applications. Expertise in the multiple technologies set to underpin future AI developments is therefore a necessity.

Alphawave Semi has customized silicon solutions optimized for diverse workloads across 64G UCIe, 224G SerDes, 800G/1.6T UALink and 800G/1.6T UEC controllers. These are deliverable as IP subsystems or tailored, silicon-proven chiplets to address all aspects of connectivity in the data center. The company has also recently unveiled a portfolio of PAM4 and Coherent-lite DSPs over optical and electrical connections for server-to-server and data center-to-data center interconnect.

New architectures and fabrics to achieve the density and performance are being achieved through the highest speed SerDes on advanced process nodes. Additionally, extremely efficient die-to-die (D2D) technologies, such as UCIe, delivers chip-to-chip connectivity not only on the same package, but solutions for the heterogeneous integration across the entire data center.

These hyper-optimized scale-up networks will link up to 1,000 GPUs to act like a single giant GPU. Multiple scale-up networks will then be connected and orchestrated over a dedicated scale-out network channel for low latency, low power, and low collisions.

“Through our unique DSP-based SerDes, manufactured using TSMC’s most advanced process nodes, our AI platform can deliver the performance required at the low-power levels needed via passive copper and low-power optical connectivity. This includes bringing optics to the XPUs and leverages the low power, high-efficiency benefits of UCIe die-to-die connectivity (below 1pJ/bit) while capturing the long reaches of optics,” said Mohit Gupta, Senior VP & GM, Custom Silicon & IP, Alphawave Semi. “Our portfolio of silicon IP subsystems are set to be the building blocks of the custom silicon and chiplets that make up AI platforms,” continued Mohit Gupta.

“The participation of Alphawave Semi in the UALink Consortium, along with their foundational IP for AI platforms, is helping advance the high-speed connectivity essential for next-generation AI infrastructure,” said Kurtis Bowman, UALink Consortium Chair. “Their integration of low-latency controllers and high-speed SerDes technology aligns well with UALink’s mission to deliver high-bandwidth, low-latency interconnects. We believe their collaboration will play a key role in driving the scalability and efficiency required to support the rapid growth of AI workloads.”

“We are delighted with our latest collaboration with Alphawave Semi to deliver this AI platform, which is a strong example of how advanced process technology and packaging can come together to enable the next wave of AI and data center innovation,” said Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC. “We will continue to work with our Open Innovation Platform® (OIP) partners like Alphawave Semi to enable semiconductor innovation that will help shape the future of compute infrastructure.”

Alphawave Semi’s AI platform includes standard and custom-form-factor chiplets, with a portfolio of proven I/O chiplet technologies. It also includes scale-up, scale-out, and 224G networks over co-packaged optical and electric connections – including via 64G third-generation UCIe and UALink with low-latency, low-power PHY and controllers. These are implemented through a strong ecosystem of foundry and SerDes expertise, connector, and component industry partners that enable the use of TSMC’s advanced 2.5 and 3D packaging techniques as well as 2 nm process nodes to create a wide variety of AI silicon and compute subsystems.