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INEMI Interim Report: Interconnection Modeling and Simulation Results for Low-Temp Materials in First-Level Interconnect
May 30, 2025 | iNEMIEstimated reading time: 1 minute
One of the greatest challenges of integrating different types of silicon, memory, and other extended processing units (XPUs) in a single package is in attaching these various types of chips in a reliable way. Key modulators for reliability are the maximum temperature that the silicon chip experiences during assembly bonding processes, interaction with chip warpage, and solder joint reliability.
INEMI’s Low-Temperature Material Discovery and Characterization for First-Level Interconnect Project has conducted simulation studies of low-temperature solder materials, including SAC305, eutectic SnBi and SnBiCuNi, using solder package structures with solder sphere and Cu pillar interconnections.
They project team will share results from these studies, including bump collapse simulation, thermal mechanical simulation and electromigration simulation. We will also talk about future plans for the project.
Webinar Speakers
Russel Kastberg (IBM), Project Co-Chair
Webinar moderator
Gokhale Shripad (Intel), Project Chair
Topic: Bump collapse modeling and simulation results
Kei Murayama (Shinko)
Topic: Electromigration modeling and simulation results
Yasuharu Yamada (IBM)
Topic: Thermal mechanical modeling and simulation results
Registration
This webinar is open to industry; advance registration is required. You will need to log into your web account (free to members and non-members) to register. If you do not have a current web account, please create one and set up your profile. If you have any questions or need additional information, please contact Masahiro Tsuriya (m.tsuriya@inemi.org).
Thursday, June 19, 2025
10:00-11:00 a.m. JST (Japan)
9:00-10:00 p.m. EDT on Wednesday,, June 18 (U.S. & Canada)
Get additional details and link to registration.
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