Talking with Tamara: Floor Planning Policies
September 4, 2025 | Andy Shaughnessy, Design007 MagazineEstimated reading time: 1 minute
Tamara Jovanovic is an electrical engineer with Masimo, a medical equipment manufacturer. She’s been designing PCBs for seven years and earned a master’s degree in electrical engineering in 2022. I asked Tamara to share her thoughts on floor planning—the challenges, techniques, and advice for designers setting up floor planning strategies.
Andy Shaughnessy: What is the objective of floor planning during PCB design?
Tamara Jovanovic: For any new circuit board design, the floor planning step typically occurs when the schematic is finalized (or nearly finalized) and before layout and routing begin. The objective of floor planning is to ensure that what you're designing is most optimized from the signal integrity perspective—ESD/EMI, as well as mechanical and thermal.
The idea is to place large components on the circuit board first, especially those that interact with mechanical features of the design and to isolate noise sensitivity on the board. This process is typically carried out by the PCB design engineer in collaboration with a mechanical engineer, using design tools to place components and align/mate them with mechanical elements, as well as to make sure there is enough separation for sensitive signals that need proper isolation/grounding.
Shaughnessy: What factors figure into the floor planning process?
Jovanovic: First and foremost, designers need to make sure that they're choosing components that will fit in the final product's mechanical enclosure and on the board shape previously agreed upon. It's also important to have an early plan for the board's layer stackup, or how many layers the board shall have and what each layer will be designated for (i.e., signal or power/ground).
Most of the time, the first components that are placed on the board are main design elements such as main processors and power ICs, which often require special design considerations and proper thermal management. Next, we have components that carry sensitive signals, such as clocks, crystals and RF parts. Those usually require careful handling when it comes to grounding and impedance, so it's always good practice to plan their placement early and ensure they are properly isolated.
To continue reading this interview, which originally appeared in the August 2025 edition of Design007 Magazine, click here.
Testimonial
"Advertising in PCB007 Magazine has been a great way to showcase our bare board testers to the right audience. The I-Connect007 team makes the process smooth and professional. We’re proud to be featured in such a trusted publication."
Klaus Koziol - atgSuggested Items
ACCM Unveils Negative and Near-zero CTE Materials for Large-Format AI Chips
04/21/2026 | Advanced Chip and Circuit MaterialsAdvanced Chip and Circuit Materials, Inc. (ACCM) has launched two new materials: Celeritas HM50, with a negative coefficient of thermal expansion (CTE) of -8 ppm/°C to offset the positive CTE and expansion of copper with temperature on circuit boards, and Celeritas HM001, with near-zero CTE and the low-loss performance needed for high-speed signal layers to 224 Gb/s and faster in artificial intelligence (AI) circuits.
FlashPCB Names Matthew Belknap Production Manager as Operations Continue to Ramp
04/21/2026 | FlashPCBFlashPCB, a leading provider of quick-turn PCB assembly, has promoted Matthew Belknap to Production Manager, following his recent start with the company earlier this year.
FlashPCB Welcomes Adam Broeckert, EIT as Manufacturing Engineer
04/20/2026 | FlashPCBFlashPCB, a leading provider of quick-turn PCB assembly, is pleased to announce the addition of Adam Broeckert, EIT, as Manufacturing Engineer.
Single Pair Ethernet (SPE): A Valuable Option for Modern Designs
04/20/2026 | Marcy LaRont, I-Connect007When it comes to designing PCBs and full systems for increasingly complex electronics hardware, who doesn’t want to reduce complexity and cost? Single-Pair Ethernet (SPE) has emerged as a solution and is gaining rapid attention across industrial electronics and PCB design because it enables Ethernet communication over a single twisted pair, replacing the traditional two- or four-pair cabling used in standard Ethernet networks. This seemingly simple shift has significant implications for designers: smaller connectors, reduced cable weight, longer reach, and the ability to carry both data and power over a single pair.
DARPA Launches HARQ Program to Integrate Diverse Qubits for Scalable Quantum Computing
04/20/2026 | DARPADARPA has launched the Heterogeneous Architectures for Quantum (HARQ) program, an effort aimed at overcoming one of the most persistent barriers in quantum computing: how to move beyond single-technology systems to achieve and scale practical, high-impact applications.