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Artificial intelligence (AI), together with machine learning (ML), is creating an unprecedented surge of computing and networking infrastructure needs. This, in turn, has dramatically increased the power consumption of computing and networking chips. Traditional design and validation methods no longer seem to cope with the new challenges; a paradigm shift is underway in how we design, optimize, and validate our system’s power distribution network (PDN).
During my career in electronics design, the first paradigm shift happened in the late 1990s, when the central processing units (CPUs) in computers grew in complexity and suddenly required tens of amperes of core current. Very early computer boards (before the 1990s) did not need any specific power distribution design. This is illustrated in Figure 1, which shows a diode-transistor logic (DTL) card from computing equipment made in the 1970s. It was on a two-sided board, with no ground plane and no bypass capacitor.
Many of us remember the prevailing rule of thumb from the 1980s: Place a 0.1 μF ceramic capacitor across the power-ground pins of each logic chip, usually in dual-in-line (DIL) package. However, by the mid-1990s, the current transients of CPU core rails required a new approach, and power-ground plane pairs replaced the power-ground traces. As a result, the number and values of bypass capacitors increased, and a systematic frequency-domain design approach was developed. It was based on a calculated impedance target for the power distribution network.
Continue reading this article in the October 2025 issue of Design007 Magazine.
