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Astera Labs Opens Israel Design Center to Boost AI Connectivity Expansion
February 13, 2026 | Astera Labs, Inc.Estimated reading time: 3 minutes
Astera Labs, Inc., a leader in semiconductor-based connectivity solutions for rack-scale AI infrastructure, announced a significant expansion of its global engineering operations with the establishment of an advanced research and development center in Israel. The new design center will accelerate the development of Astera Lab’s next-generation scale-up fabrics for high-bandwidth connectivity protocols, while also advancing technical research and development to address memory bottlenecks in AI training and inference applications. Semiconductor industry veteran Guy Azrad, senior vice president of engineering and general manager of Astera Labs Israel will lead the new Israel operations, and will be supported by Ido Bukspan as vice president of ASIC engineering.
Astera Labs is expanding its global engineering footprint with the new Israel design center as a strategic investment in one of the world’s premier semiconductor ecosystems. The new center creates an end-to-end facility for advanced research and development of connectivity solutions in Israel that aims to solve critical data, network, and memory bottlenecks. Through collaborations with leading Israeli universities and the venture ecosystem, the design center is expected to serve as a hub to advance technologies critical to support next-generation AI infrastructure worldwide.
“We’re building an engineering team with a strong focus on execution, covering hardware, silicon, and software solutions, to support the growing adoption of Astera Labs’ Intelligent Connectivity Platform,” said Guy Azrad, senior vice president of Engineering and general manager of Astera Labs Israel. “With offices in Tel Aviv and Haifa, the new Israel design center will look to tap into the region’s world-class engineering talent to focus on the full chip design flow—from architecture through production, including software and system design for cutting-edge AI fabrics and emerging inference applications.”
Guy Azrad brings extensive semiconductor leadership experience in high-speed networking, compute, and Ethernet technologies to his role as general manager of the Israel design center. He most recently served as vice president of chip design engineering at Google, where he led silicon development for compute applications. Prior to Google, he held senior engineering leadership roles at Marvell, where he was senior vice president of the company’s global Ethernet switching division, overseeing development of advanced networking solutions deployed across data centers worldwide. His career spans deep expertise in developing advanced networking system-on-chips (SoCs), building and scaling large-scale chip design organizations across multiple geographies, and delivering complex silicon solutions from architecture through production. Azrad has been instrumental in bringing multiple generations of high-performance networking products to market.
The Israel design center expansion is further strengthened by the addition of Ido Bukspan, who joins Astera Labs as vice president of ASIC Engineering to support the company’s scale-up fabric development initiatives. Bukspan brings over two decades of networking and semiconductor expertise from his combined tenure at Mellanox Technologies and NVIDIA, where he spent 20+ years and rose to the position of senior vice president of Chip Design, building high-performance InfiniBand, Ethernet, and NVLink solutions that helped transform the data center industry and enable modern AI infrastructure. Most recently, Bukspan served as CEO of Pliops, a data acceleration technology company, where he led the organization’s strategic direction and product development for KV-cache applications.
“Israel has been defining networking innovation for decades, from those formative years when we were proving what was possible to today’s AI-driven transformation,” said Ido Bukspan, vice president of ASIC Engineering at Astera Labs. “I see the same drive, the same intensity to deliver highly performant connectivity solutions at Astera Labs. Together, we’re taking AI connectivity to the next level. Come join us.”
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Cadence, NVIDIA Expand AI & Accelerated Computing Partnership
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Teradyne Acquires TestInsight, Accelerating Time to Market for AI and Data Center Devices
04/16/2026 | BUSINESS WIRETeradyne, Inc., a leading provider of automated test equipment (ATE) and advanced robotics, announced it has acquired TestInsight, a leading provider of semiconductor test development, validation, and conversion software widely used across the industry.
Cadence, Google Scale AI Chip Design with ChipStack on Google Cloud
04/16/2026 | Cadence Design SystemsCadence, an industry leader in AI-driven computational software for semiconductor and system design, announced a strategic collaboration with Google to optimize the Cadence® ChipStack™ AI Super Agent with Gemini on Google Cloud.
ESD Alliance Reports Electronic System Design Industry Posts $5.5 Billion in Revenue in Q4 2025
04/15/2026 | SEMIElectronic System Design (ESD) industry revenue increased 10.3% to $5,466.3 million in the fourth quarter of 2025 from the $4,955.2 million registered in the fourth quarter of 2024, the ESD Alliance, a SEMI Technology Community, announced today in its latest Electronic Design Market Data (EDMD) report.