SMTA WLPS 2026 Review: Shifting Microelectronic Package Development

Estimated reading time: 3 minutes

The Surface Mount Technology Association (SMTA) hosts a number of timely events each year to focus on key technologies. The most recent, the 2026 Wafer-Level Packaging Symposium, held in San Francisco this February, brought together prominent technologists and manufacturers involved in microelectronic package development and related infrastructure.

The three-day event included several timely technical presentations, concluding on Day 3 with two professional development courses: “The Critical Role of PCB Strain Measurement in Ensuring Reliability of Advanced Wafer-Level Packages” by Takahiro James Hara with Kyowa America, and “Current and Future Challenges and Solutions in AI and HPC System Thermal Management” by Gamal Refai Ahmed from GAMAa63.

Conference Chair Thom Gregorich of Zeiss SMT led the two-day technical program, observing that package technology is shifting from monolithic multiple-function single-die packaging to the flexibility offered with system-level products using multiple chiplet dies and 2.5D and 3D package methods. Ashkan Seyedi of NVIDIA delivered the Day 1 keynote, “Pioneering System Integration for Tomorrow’s AI Workloads,” which focused on thermal management solutions the company has developed for controlling large-scale data centers and AI factories.

Speakers in the technical program included experts from both domestic and international companies covering a wide range of topics related to wafer-level, panel-level and heterogenous system-in-package challenges:

• Muhammed Hussain from Purdue University in Austin, Texas, emphasized the value of education and formal training, with an overview of their “Semiconductor 101” program.
• Johnathan Adlilla from BESI focused on hybrid thermo-compression D2D, D2W, and D2P bonding and the challenge of joining 10-micron terminal pitch chiplet die elements.
• Georghe Stan from the National Institute of Standards and Technology (NIST) spoke on the processes involved in hybrid bonding, aligning and joining.
• Steven Martell presented initial results of the organization’s RDL Adhesion Project, plus the new SEMI Guideline for testing peel strength of fine-line conductors on silicon wafers.
• David Box with Skywater gave a presentation detailing the advantages and practical benefits of domestic sourcing for advanced wafer level packaging services.
• Charles Woychik from NHanced Semiconductors presented an update on the global outlook compared to the U.S. focus on outsourcing assembly and test for WLP components.
• Raj Varma, representing Gel-Pak, detailed what they call a “bio-inspired,” textured polymer base-layer tray carrier design compatible with traditional robotic pick-and-place or die-attach systems.
• Deepak Pandey, Yield Engineering Systems, described a unique polymer brush (PB) coating process they developed for glass interposer surfaces with complex topographies.
• Vinayak Pandey from KLA Corporation addressed process control challenges for advanced packaging developed for AI and hybrid bonding applications.
• Takenori Fujiwara with Toray Industries gave a detailed view of photo-definable dry film adhesive and a temporary de-bonding adhesive for wafer-level advanced packaging.
• Kaveh Hosseini, representing Intel Corporation, shared an example of their work on packaging next-generation AI, co-packaged optics, and progress in advanced package integration.
• Martin Kainz from BESI described their non-flux thermo-compression bonding process for ultrafine-pitch Cu-to-Cu hybrid joining.
• Srinidhi Ramamoorthy with Applied Materials shared the company's progress in fine-pitch hybrid bonding and fusion bonding for chiplet-configured architectures.
• Ami Eitan, ASMPT Semi Solutions, provided a detailed overview of die-bonding applications, including chip-on-substrate (CoS), chip-on-wafer bonding (CoW), and hybrid bonding (HB) technologies.

The Wednesday keynote featured Ritesh Jain, Lightmatter, who gave a presentation on 3D photonic interposer applications connecting XPUs and switches, enabling unmatched speed in AI compute performance scaling.

• Taro Arimoto with OSHIO in Japan shared his company’s hybrid excimer VUV-based smear removal process for high-density fine wiring in semiconductor package substrates.
• Tadas Kildusis from Akoneer shared his company's narrow Cu writing technology that enables the formation of conductive circuits on dielectric polymers, ceramics, glass, and silicon. 
• E. Jan Vardaman, TechSearch International, Inc. addressed two market segments, low-density panel level fan-out and high-density multichip panel level packaging. Where do they fit?

The final event of the technical conference was a panel discussion, chaired by Vardaman, on challenges in wafer-level packaging and the status of glass- or polymer-based glass substrates as alternatives to silicon.

Vern Solberg is a long-time member of the SMTA and a ‘Founders Award’ recipient, participating as both a presenter of technical papers and serving as a professional development course instructor on topics related to SMT and Microelectronic Design for Manufacturing.