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Wolfspeed Launches Next-Gen AI Data Center Packaging with 300mm SiC Technology
March 26, 2026 | WolfspeedEstimated reading time: 2 minutes
Wolfspeed, Inc. , a global leader in silicon carbide technology, announced that its 300 mm silicon carbide (SiC) technology platform could serve as a foundational materials enabler for advanced AI and high‑performance computing (HPC) heterogeneous packaging by the end of this decade.
“As AI workloads continue to increase package size, power density, and integration complexity, we believe new materials foundations will be increasingly important to extend advanced packaging roadmaps,” said Elif Balkas, Chief Technology Officer at Wolfspeed. “Our 300 mm silicon carbide platform is designed to align SiC’s material advantages with industry‑standard manufacturing infrastructure and expand the solution space for next‑generation AI and HPC packaging architectures.”
Building on its January 2026 milestone of successfully producing a single‑crystal 300 mm SiC wafer, Wolfspeed is engaging AI ecosystem partners to explore how 300 mm SiC substrates could help address the thermal, mechanical, and electrical performance barriers increasingly limiting next‑generation AI and HPC packaging architectures.
Driven by rapidly scaling AI workloads, data center integration roadmaps are pushing package sizes, power densities, and functional complexity beyond the limits of conventional materials. Wolfspeed’s 300 mm SiC platform is designed to help address these challenges by combining high thermal conductivity, mechanical robustness, and favorable electrical properties within a scalable manufacturing format aligned to existing 300 mm semiconductor infrastructure.
Through its ongoing partner evaluation program, Wolfspeed is collaborating with foundries, OSATs, system architects, and research institutions to assess technical feasibility, performance benefits, reliability, and integration pathways. This collaborative approach is intended to accelerate learning, help de‑risk adoption, and help prepare the industry for the hybrid silicon carbide–silicon packaging architectures required by future AI workloads.
A 300 mm SiC wafer format aligns advanced packaging materials with leading edge semiconductor fabrication and wafer level packaging processes, leveraging existing industry toolsets and infrastructure. This is intended to enable repeatable, high volume manufacturability while supporting cost scaling and ecosystem compatibility. In addition, the 300 mm format can enable fabrication of larger interposer and heat spreader components, supporting the industry’s trajectory toward increasingly large package form factors and more complex multi-component semiconductor assemblies.
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MacDermid Alpha to Address Silver Price Volatility Solutions at ECTC 2026
05/15/2026 | MacDermid AlphaAs volatile silver prices continue to place pressure on semiconductor packaging costs and supply chain predictability, MacDermid Alpha Electronics Solutions will highlight material strategies that help manufacturers reduce dependence on silver without sacrificing reliability, thermal performance, or manufacturing efficiency.
What Heterogeneous Integration Means for EMS Providers
05/14/2026 | Nolan Johnson, I-Connect007Dr. Ravi Mahajan, an Intel Fellow and Director of Intel’s Technology and Pathfinding group, delivered a keynote at the APEX EXPO 2026 technical conference on using heterogeneous integration (HI) as a strategy and on how advanced packaging technology serves as the technical apex for implementing that strategy. Mahajan’s previous papers and industry presentations on such topics as interconnect density, signal integrity, power delivery, thermal path, and assembly yield as system-level constraints confirm him as an expert on package optimization.
System Architecture Beyond the Die With Advanced Packaging as the Scaling Factor
05/14/2026 | Chetan Arvind Patil, Marvell TechnologyIn conventional monolithic semiconductor design, system integration was achieved within a single die and constrained by reticle limits. Compute cores, cache, memory controllers, and input output (I/O) interfaces were all co-optimized on a single process node, with performance closely tied to transistor density and on-die interconnect efficiency. This monolithic system-on-chip (SoC) approach enabled low-latency communication and relatively straightforward power delivery. However, as design for compute-intensive SoCs approaches reticle limits and advanced-node costs increase, the ability to continue scaling within a single die begins to diminish.
I-Connect007 Announces Upcoming Issue of Advanced Electronics Packaging Digest
05/13/2026 | I-Connect007The next issue of Advanced Electronics Packaging Digest examines the materials, architectures, and integration strategies shaping the next phase of electronics innovation, from reinforcement materials under thermal and frequency pressure to heterogeneous integration and advanced packaging as a system-level scaling factor.
ASE, WUS Announce Strategic Collaboration to Build Advanced AI Packaging Hub in Kaohsiung
05/08/2026 | ASE GroupAdvanced Semiconductor Engineering, Inc. (ASE) and WUS Printed Circuit Co., Ltd. (WUS) announced today a strategic collaboration for the construction of a state-of-the-art manufacturing facility in the Nanzih Technology Industrial Park, Kaohsiung.