Synergy Quantum Unveils Quantum-Safe Silicon IP Cores for RISC-V-Based SoCs

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Synergy Quantum announced a portfolio of quantum-safe silicon IP cores for RISC-V-based system-on-chip designs, enabling semiconductor companies, processor developers and equipment manufacturers to integrate post-quantum cryptographic capabilities directly into ASICs, FPGAs and embedded platforms. Developed by Synergy Quantum, the IP portfolio combines post-quantum cryptographic acceleration with secure boot, hardware-bound identity, protected key handling, firmware verification and device-attestation capabilities.

The portfolio is designed for integration into RISC-V-based SoCs as dedicated security components, cryptographic coprocessors or building blocks within a broader hardware root-of-trust subsystem.By placing quantum-safe cryptographic functions directly in silicon, the architecture can improve performance, reduce dependence on software-only implementations and provide stronger isolation for sensitive keys and intermediate cryptographic values.

Bringing quantum-safe security into RISC-V silicon

RISC-V is increasingly being adopted across embedded systems, industrial platforms, communications infrastructure, defence electronics, automotive systems and custom semiconductor designs.Many of these devices are expected to remain operational for years or even decades. Their security architectures must therefore be capable of supporting the transition from classical cryptography to post-quantum security.

Synergy Quantum's silicon IP portfolio is intended to help RISC-V developers address this transition at the processor and SoC level. Instead of treating post-quantum cryptography as an application-layer upgrade, the IP enables key establishment, signature verification, secure boot and device-trust operations to be implemented as dedicated hardware functions within the chip.The architecture supports industry-standard SoC interconnects and processor-extension interfaces, enabling the cores to be integrated with existing RISC-V processors and custom SoC architectures without requiring a complete redesign of the host platform.