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Advanced Electronics Packaging Digest

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Stay ahead of the technologies shaping the future of electronics with our latest newsletter, Advanced Electronics Packaging Digest. Get expert insights on advanced packaging, materials, and system-level innovation, delivered straight to your inbox.

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Suggested Items

3 Key Takeaways from The Printed Circuit Assembler's Guide to... Via Structures: Reflow Process Survivability, Reliability, and Robustness

09/22/2026 | I-Connect007
As PCB technology has evolved, the structures being evaluated become more complex. But have the methods used to determine their reliability evolved at the same pace? In The Printed Circuit Assembler's Guide to... Via Structures: Reflow Process Survivability, Reliability, and Robustness, Bob Neves challenges some long-held assumptions about how the electronics industry evaluates PCB via structures. He draws on decades of reliability experience, and examines not only how we test, but what those tests actually tell us.

Custom Interconnect to Exhibit at Microelectronics UK 2026

09/21/2026 | Custom Interconnect Ltd
Custom Interconnect is excited to exhibit at Microelectronics UK 2026 on Stand H60, at ExCeL London on 29 and 30 September.

Teradyne Introduces Iris 100 MicroLED Test System

09/21/2026 | BUSINESS WIRE
Teradyne, Inc., a leading provider of automated test equipment and advanced robotics, announced Iris 100, a production-ready optical test platform for microLED devices.

Würth Elektronik Receives First TDAP Stage 2 Certificate for EMC Chokes

09/17/2026 | Würth Elektronik
The Würth Elektronik lab at its Quality Design Center Asia in Shenzhen has been awarded the world’s first TDAP Stage 2 certificate for the product “choke for suppressing electromagnetic interference” by VDE Prüf- und Zertifizierungsinstitut GmbH.

Advanced Packaging and the New Scaling Walls

09/17/2026 | Chetan Arvind Patil, Marvell Technology
Advanced packaging is becoming the foundation for semiconductor scaling in the AI era. As monolithic processors encounter practical limits around reticle size, yield, memory bandwidth, power, and cost, the industry is moving toward architectures built from multiple compute dies, HBM stacks, I/O chiplets, and heterogeneous packaging solutions. The result is that semiconductor scaling is no longer determined only by how much functionality can be integrated into a single die, but by how much silicon can be integrated efficiently within a package.
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