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Design for Assembly: High-density Circuits for Hand-held and Portable Products
December 31, 1969 |Estimated reading time: 23 minutes
Chip scale ball grid array (BGA) packaging is seen by many as a viable answer to the space restrictions necessitated by new generations of hand-held and portable electronics products, as well as to the demand for their higher functionality and performance. By Vern Solberg
Figure 1. IEC standards for land pattern geometry for two terminals, rectangular capacitor and resistor devices, can vary to meet specific product applications (see Table 1).
Performance and reliability are given high priority when developing electronics products for today's value-driven market. To compete in this market, developers must focus on assembly efficiency as well, in order to control manufacturing costs. Technological advances and the growing complexity of electronics products are creating the demand for higher density circuit fabrication methodology. When the design requires extensive use of surface mount, fine-pitch and array packaged integrated circuits (IC), a higher density circuit board with finer line width and closer spacing may be required. Looking toward the future, however, companies already supplying micro-via, sequential build-up circuit boards are investing heavily in expanding capacity. These companies recognize the current trends for smaller packaging of portable and hand-held electronics. The communication and personal computing product industry growth alone is leading the market throughout the world.
Developers of high-density electronics increasingly are challenged by several factors: physical (finer lead spacing on complex devices), financial (placement must be very precise) and environmental (many plastic packages absorb moisture, causing cracking during assembly processing). Physical issues also include the attachment process complexity and finished product reliability. Further financial decisions must be made regarding how the product will be manufactured and assembly equipment efficiency. The more fragile leaded devices, such as the 0.50 and 0.40 mm (0.020 and 0.016") lead pitch shrink quad flat pack (SQFP) may pose a challenge to assembly specialists in maintaining a consistent assembly process yield. The most successful development programs are those that have implemented process proven circuit board design guidelines and process proven land pattern geometry.
Figure 2. The IEC land pattern standard for ribbon and gull-wing leaded devices defines three possible variations to meet the user application (see Table 2).
Environmentally, the land pattern geometry can be different based on the type of soldering used to attach the electronic part. Wherever possible, land patterns are defined in such a manner that they are transparent to the attachment process being used. Whether parts are mounted on one or both sides of the board, subjected to wave, reflow or other soldering types, the land pattern and part dimensions should be optimized to ensure proper solder joint and inspection criteria. Although patterns are defined dimensionally and because they are a part of the printed board circuitry geometry, they are subject to the producibility levels and tolerances associated with plating, etching, assembly or other conditions. The producibility aspects also pertain to soldermask use and the registration required between the soldermask and conductor patterns.
Land Pattern RequirementsThe International Electrotechnical Commission (IEC) 61188 standard recognizes the need to have different goals for the solder fillet or land protrusion conditions. The new international standard acknowledges two basic methods of providing information for developing land patterns:
1) Exact details based on industry component specifications, board manufacturing and component placement accuracy capabilities. These land patterns are restricted to a specific component and have an identifying land pattern number.
2) Equations can be used to alter the given information to achieve a more robust solder connection, when used in particular situations in which the equipment for placement or attachment are more or less precise than the assumptions made when determining the land pattern details.
The standard defines maximum, median and minimum material conditions for the land protrusions used to develop the land pattern for mounting various lead or component terminations. Unless otherwise indicated, the sectional standards identify all three "expectation goals" as level 1, level 2 or level 3.
Level 1: Maximum For low-density product applications, the "maximum" land pattern condition has been developed to accommodate wave or flow solder of leadless chip devices and leaded gull-wing devices. The geometry furnished for these devices, as well as inward and "J"-formed lead contact device families, may provide a wider process window for hand soldering and reflow solder process.
Level 2: Median Products with a moderate level of component density may consider adapting the "median" land pattern geometry. Very similar to the IPC Association Connecting Electronics Industries (IPC)-SM-782 standard land pattern geometry, the median land patterns furnished for all device families will provide a robust solder attachment condition for reflow solder processes and should offer a condition suitable for wave or flow soldering of leadless chip and leaded gull-wing type devices.
Level 3: Minimum Products with high component density (typical of portable and hand-held product applications) may consider the "minimum" land pattern geometry variation. Minimum land pattern geometry selection may not be suitable for all product use categories. Before adapting the minimum land pattern variations, the user should consider product qualification testing based on the conditions shown in tables.
The land pattern geometry supplied in IPC-SM-782 as well as that furnished in IEC 61188 should accommodate both component tolerance and process variables. Although the land patterns in the IPC standard have furnished the user with a robust interface for most assembly applications, some companies have expressed the need to adapt minimal land pattern geometry for portable, hand-held electronics and other unique high-density applications.
The International Land Pattern Standard (IEC 61188) recognizes the requirements of higher component density applications and provides information on land pattern geometry used for specific product categories. The information's intent is to provide the appropriate size, shape and tolerance of surface mount land patterns to ensure sufficient area for the appropriate solder fillet, and also to allow for inspection, testing and rework of those solder joints.
Three land pattern geometry variations typical of that illustrated in both Figure 1 and Table 1 are supplied for each of the device families: maximum land protrusion (Level 1), median land protrusion (Level 2) and minimum land protrusion (Level 3).
Solder joint toe, heel and side fillets must address the tolerance of component, board and placement accuracy tolerances (sum of the squares). As shown in Figure 2, the minimum solder joint or land protrusion is increased by the amount that the tolerance variation does not use up (Table 2).
If the user of these land patterns desires a more robust process condition for placement and soldering equipment, individual elements of the analysis may be changed to new and desired dimensional conditions. This includes component, board or placement accuracy spread, as well as minimum solder joint or land protrusion expectation (Tables 3, 4, 5 and 6).
Profile tolerance methodology is used for lands in a manner similar to that of the components. All land tolerances are intended to provide a projected land pattern with individual lands at maximum size. Unilateral tolerances are intended to reduce the land size, thus resulting in a lesser area for solder joint formation. To facilitate companion dimension systems, the land pattern is dimensioned across outer and inner extremities.
The dimensioning concept in this standard uses limiting dimensions and geometric tolerancing to describe the allowable maximum and minimum dimensions of the land pattern. When lands are at their maximum size, the result may be a minimum acceptable space between lands; conversely when lands are at their minimum size, the result may be a minimum acceptable land pattern necessary to achieve reliable solder joints. These thresholds allow for gauging the land pattern for go/no-go conditions.
Given that the land pattern geometry is correct and the finish on the circuit structure meets all criteria specified, solder defects should be minimized; however, defects still can occur due to material and process variables. The designer developing the land pattern for fine pitch must establish the minimum toe and heel required for a reliable solder connection as well as allowing for both the maximum and minimum (or least) material condition on the device package features.
BGA and Chip Scale Packaging (CSP)BGA packaging has been developed to be compatible with current solder attachment technologies. The plastic and ceramic BGA devices have a relatively wide contact pitch (1.50, 1.27 and 1.00 mm) compared to the chip scale BGA having 0.50, 0.65 and 0.80 mm grid pitch. Both BGA and fine-pitch BGA devices are less prone to damage than fine-pitch lead-frame packaged ICs, and BGA standards allow for selective depopulation of contacts to meet specific input/output (I/O) requirements. When establishing contact layout and pin assignment for BGA devices, the package developer must consider chip design as well as the size and shape of the die. Another issue addressed while planning pin assignment is the die orientation (die bond pads facing up or facing down). The die "face up" configuration typically is adapted when the supplier is using chip-on-board (interposer) technology.
Figure 3. Land patterns for BGA may be defined by the etched pattern, free of soldermask or with soldermask overlapping the land perimeter (soldermask defined).
Device construction, as well as the combination of materials used in its manufacture, is not defined in the industry standards and guidelines. Each manufacturer will attempt to qualify their particular configuration to the application defined by the user. Consumer products for example, may have a relatively benign working environment while products used for industrial or automotive applications often must operate in somewhat more stressful conditions. Depending on the physical characteristics of material selected for manufacturing the BGA, flip chip or wire-bond technologies may be employed. Because the die attachment structure is a rigid material, the die bond or attachment site generally is centered with conductor paths furnished to route the signal from the die bond pads to the ball contact array matrix.
The grid array package outlines detailed in this document are furnished in Joint Electronic Devices Engineering Council (JEDEC) Publication 95. The square BGA, JEDEC MS-028 defines a smaller family of rectangular plastic BGA devices with 1.27 mm contact pitch. The overall outline specification for the array device allows a great deal of flexibility as far as lead pitch, contact matrix pattern and construction. JEDEC MO-151 defines a diverse family of plastic packaged BGA. The square outline covers a size range from 7.0 through 50.0 mm and three contact pitch variations 1.50, 1.27 and 1.00 mm.
Ball contacts may be distributed in a uniform pattern with even or odd numbers of column and row array. Although the array must remain symmetrical to the overall package outline, depopulation of contact locations or contacts within a zone is permitted at the discretion of the device manufacturer.
Chip Scale BGA VariationsRecently developed JEDEC BGA guidelines for "fine-pitch" and "real chip size" IC packaging address many of the physical attributes and provide flexibility to the package supplier in the form of "variation." The first document approved by JEDEC JC-11 for the fine-pitch BGA device category is the Registered Outline MO-195, a uniform square package family with a basic 0.50 mm pitch contact array.
The package size ranges from 4.0 to 21.0 mm and the overall height (defined as "thin profile") is limited to 1.20 mm maximum from the mounting surface. The following examples represent some of the other variations being considered for future standards activity.
Ball pitch and ball size will influence circuit routing efficiency as well. Many companies have elected not to adapt the 0.50 mm pitch for lower I/O CSP applications, choosing instead a more relaxed contact pitch. The coarser ball pitch may relieve end users' need for adapting more complex printed circuit board (PCB) technology.
The 0.50 mm array contact pitch is the minimum recommended by JEDEC. The contact diameter is specified as 0.30 mm with a tolerance range as small as 0.25 or as high as 0.35 mm. Most BGA applications adapting the 0.50 mm pitch variation, however, will rely on subsurface routing of the circuit paths. The space between land patterns as small as 0.25 mm in diameter are only wide enough for interconnecting a single 0.08 mm (0.003") wide circuit (or one row into the array). Distributing a number of redundant power and ground contacts to the perimeter of the array and selective or interstitial depopulation will provide a limited penetration of the array matrix. These higher I/O applications more likely will rely on multi-layer, blind or plated closed via-in-pad technology.
Consider Package TechnologyDevice performance, both environmental and electrical, may be as significant an issue as the package size. The package technology adapted for the high-density, high I/O applications first must meet environmental criterion. Those using a rigid interposer structure fabricated from ceramic or organic laminate, for example, cannot closely match the silicon die outline. The interconnection between the lead bond sites around the device perimeter must flow inward. One practical advantage of the µBGA* package structure is its ability to provide all electrical interfacing within the silicon die outline.
The µBGA employs a high-grade polyamide film as its base structure and a semi-additive copper plating process to complete the interconnect between the aluminum bond site on the die and the ball contact site on the polyamide interposer. The unique combination of compliant materials enables the device to withstand extremely harsh environments. This package has already been qualified by leading IC manufacturers to meet applications having a wide range of operating environments.
More than 20 leading IC manufacturers and packaging service providers have adapted the µBGA package. Defined as a "face-down" package, the device outline closely matches the die outline and the aluminum bond pads on the die are positioned toward the ball contacts and PCB surface. This configuration has the widest acceptance in the industry because of its established infrastructure and unequaled reliability. The unique system of materials and lead design of the µBGA package is physically compliant, compensating for the wide differences in the coefficient of thermal expansion between the silicon die and the PCB structure.
Attachment Site PlanningThe attachment site or land pattern geometry recommended for BGA devices typically is round, with the diameter adjusted to meet contact pitch and size variation. The land diameter should be no larger than the diameter of the contact or ball on the package and often is 10 percent smaller than the normal diameter specified for the ball contact. Refer to IPC-SM-782 Section 14.0 or the manufacturer's specification before finalizing land pattern array and geometry.
Two methods are used for defining the attachment site: pad or copper defined, and soldermask defined as illustrated in Figure 3.
Copper Defined Land Pattern Land patterns defined by the etched copper. Soldermask clearance should be a minimum of 0.075 mm from the etched copper land. For applications requiring a clearance that is less than recommended, consult with the printed board supplier.
Soldermask Defined Land Pattern If soldermask defined patterns are used, adjust the land pattern diameter accordingly to ensure mask coverage.
The land pattern spacing or pitch on BGA devices are "basic" and therefore non-accumulative; however, placement accuracy and PCB fabrication tolerances must be considered. As noted, the land pattern for BGA generally is round, soldermask defined or etch (mask off pad) defined. Although the larger pitch BGA will accommodate space between lands for circuit routing, higher density and higher I/O devices will rely on plated via hole to route the circuit to subsurface layers. The land pattern geometry shown in Table 7 recommends a diameter equal to or slightly smaller than the nominal standard contact or ball diameter.
Some companies have attempted to maintain a constant contact diameter for all fine-pitch BGA applications. However, because manufacturers of the 0.65 and 0.80 mm contact pitch devices have been allowed optional ball and contact diameter variations, the designer should refer to the specific suppliers specification before establishing land pattern diameter. The larger ball and land diameter may restrict circuit routing of higher I/O devices. The land pattern geometry for some BGA device families may not allow a wide enough spacing to clear more than one or two circuit paths. The 0.50 mm pitch BGA, for example, will not allow even a single circuit greater than 0.002 or 0.003". Those adapting the fine-pitch BGA package variations may find the via-in-pad (microvia) more practical, especially if the component density is high and circuit routing must be minimized.
Features Required for Assembly Process EfficiencyTo accommodate precise registration of the stencil for fine-pitch surface mount devices (SMD), some means of vision or camera-assisted alignment is required. The globally located fiducial targets are used for both precise stencil alignment to the board for accurate solder paste printing and as a reference in accurate SMD placement. The stencil machine's camera system automatically will align the board to the stencil pattern for precise solder paste transfer.
For those systems using automated vision alignment of stencil to board, the board designer must furnish at least two global fiducial targets within the pad layer design file (Figure 4). Local fiducial targets must be furnished on each assembly unit within the panel as well, to aid automated device placement. Additionally, one or two targets typically are provided for each fine-pitch quad flat pack (QFP), thin small-outline package (TSOP) and high I/O fine-pitch BGA device.
A common fiducial size is preferred at all locations. Although shape and size can be customized for unique applications, most equipment manufacturers have agreed on a 1.0 mm (0.040") diameter solid land. The land must be free of soldermask to ensure that the camera can make a quick identification. In addition to the fiducial targets, the board must include a number of tooling holes for secondary assembly related operations. The panel should be furnished with two or three tooling holes and each board unit furnished with a minimum of two tooling holes. Typically, the size is specified by the assembly specialist (0.65 mm is common) and should be specified to be plating-free.
In regard to the fiducials furnished on the solder paste stencil fixture, some systems look at the top surface of the stencil while others look up from the lower surface. The global fiducials for this application are only partially etched into the stencil material surface and filled with black epoxy.
Specifying Surface Finish and CoatingsSelecting the specific type of surface finish or plating methodology for device attachment can improve assembly process yield but may positively influence the PCB fabrication cost as well. Electroplating a tin or tin/lead alloy circuit pattern over the copper foil as an etch resist is a very common fabrication method. The subtractive method (chemical etch) of selectively removing copper continues to be in wide use throughout the PCB industry. Because the tin/lead plated conductor traces convert to a liquid state when exposed to temperatures above 195°C, most surface mount boards using reflow solder technology are specified with soldermask over bare copper (SMOBC) to retain a flat uniform surface under the mask material. When SMOBC boards are processed, the tin or tin/lead is chemically stripped, leaving only the copper conductors and component attachment sites free of plating. Copper conductors are coated with epoxy or polymer soldermask to prevent exposure to solder assembly related processes. Although the circuit traces are coated with a soldermask, the designer also must define the finish for those features (device attachment sites) not covered by the mask. Plating and coating options include alloys and chemistry. The following examples are typical of alloy plating methods widely used in the fabrication industry.
Typical applications requiring a preconditioned attachment site are ultra-fine-pitch QFP devices. A tape automated bond (TAB) device for example, may have a lead pitch below 0.25 mm. By furnishing 700 to 800 µ" of tin/lead alloy on these sites, the assembly specialist can apply a small amount of flux, position the part and reflow solder the device using a thermode (hot bar), hot air/gas, laser or soft beam light source. Tin/lead alloy selectively plated or retained at specific attachment sites will accommodate reflow attachment of the ultra-fine-pitch TAB package.
With the hot air leveling method, tin/lead is applied to the board after soldermask application. Coated boards are cleaned, fluxed and dipped into molten solder and while the alloy is still in a liquid state, excess material is blown off the contact surface, leaving an alloy coated surface. The hot air solder leveling (HASL) plating process is used widely and generally is compatible with reflow solder assembly processes; however, inconsistent solder volume and flatness may not be suitable for boards using fine-pitch devices.
Fine-pitch SQFP, TSOP and fine-pitch BGA devices require a very uniform and flat surface finish. As a means of controlling the uniform volume of solder paste at the attachment site of fine-pitch devices, the surface must be as flat as possible. To ensure flatness, many companies use nickel alloy over copper followed by a very thin coating of gold alloy to retard oxidation.
Electroless nickel/gold is applied over the exposed bare copper after the soldermask coating process. With this process, the fabricator typically will use the tin/lead plated circuit pattern as an etch resist, strip the tin/lead after etching, but instead of applying solder alloy to the exposed attachment sites and holes, the boards are immersion coated with the nickel/gold alloy.
According to IPC-2221, Generic Standard on Printed Board Design, the recommended electroless nickel thickness is from 2.5 to 5.0 µm (1.3 µm minimum) while the recommended immersion gold thickness is from 0.08 to 0.23 µm
A word of caution regarding gold alloy and solder processing: If the gold plating exceeds 0.8 µm (3 µ") in thickness, the gold to tin/lead ratio may cause embrittlement of the finished solder joint. Embrittlement will result in excessive cracking during thermal cycling or other physical stress the assembled board may be exposed to.
Alloy Plating AlternativesAdding solder alloy to the board after soldermask application is costly and subjects the substrate to extremely stressful conditions. With tin/lead coating for example, the board is thrust into molten solder, then extracted and blasted with air to remove excess tin/lead material. Thermal shock can cause delamination of the substrate structure, damage to plated holes and defects that may affect long term-reliability. Ni/Au plating, although less stressful, is not a technology that is available from all board fabricators. As an alternative to plating, many companies have found success, economic advantage and a flat attachment surface with organic preservatives or pre-flux coatings over bare copper.
Figure 4. To accommodate automated assembly, fiducial targets must be furnished on the surface of the circuit board structure.
As a means of retarding oxide growth on the bare copper attachment sites and via/test pads, a special preservative or inhibitor coating is applied to the board. Organic/nitrogen coating materials such as Benzotriazole and Imidazole are developed to replace the alloy finishes described and are available under trademark names from several sources. In North America, one product in wide use is the ENTEK PLUS CU-106A. This coating is compatible with most organic flux soldering material and can continue its protective characteristics through three to four exposures to high temperatures often experienced during assembly processes. Multiple exposure capability is important. When SMDs are to be attached to both primary and secondary sides of the assembly, a double exposure to reflow soldering temperature occurs. Multiple assembly steps typical of mixed technology also may include exposure to wave or other solder processes.
General Cost ConsiderationsCosts associated with plating or coating PCBs are not always defined in detail. Some suppliers feel that the cost deference between the methods is such a small proportion of the overall unit price that defining costs is not significant. Others may apply a premium to costs not within their capability because boards must be sent outside for final processing. One company in California, for example, ships boards to a company in Texas for Ni/Au plating. Premiums for this extra handling may not be defined clearly as an extra charge to the customer; however, overall board cost is affected.
Each of the plating and coating processes has advantages and disadvantages. The designer and manufacturing engineer must weigh each factor carefully through testing or process yield evaluation. Issues one must consider when specifying the PCB fabrication have economical as well as process tradeoffs. For fine line, high-component density or fine-pitch technology and µBGA, flat topography is a must. Land pattern surface finish can be plated or coated but assembly processes and economics must be weighed.
Of all the coating and plating options noted, Ni/Au is the most versatile (as long as the gold thickness is below 5 µ"). The advantage the plating processes have over preservative coatings is shelf life, permanent coverage of copper on vias or other features not exposed to a solder process and contamination resistance. Although tradeoffs between surface finish characteristics will influence final selection, availability and overall PCB cost most likely will define the final selection. HASL processes traditionally have dominated the PCB industry in North America, but surface uniformity (flatness) is difficult to control. A controlled assembly process for fine-pitch device soldering relies on a flat uniform attachment site. Fine-pitch includes the TSOP, SQFP and µBGA component families. If fine-pitch devices are not used on the assembly, using the HASL process is a viable option.
Soldermask RequirementThe soldermask's role in controlling solder defects during the reflow process is significant and PCB designers should attempt to minimize clearance or air gap around land pattern features. Although many process engineers prefer that soldermask separates all land pattern features on the board, the lead spacing and pad size of fine-pitch devices will require special consideration. While the non-partitioned soldermask opening or window on a four-sided QFP may be acceptable, it may be more difficult to control solder bridging between device leads. In regard to soldermask for BGA, most companies furnish a mask that is clear of the land pattern but covers any features between lands to prevent solder bridging. Most surface mount PCBs are coated with soldermask, but soldermask coating, if greater than 0.04 mm (0.0015") thick, can affect solder paste application. Surface mount PCBs, and especially those using fine-pitch devices, require a low-profile photo-imaged soldermask. The mask material must be applied with either a liquid (wet) process or laminated as a dry film. Dry film soldermask material is supplied in 0.07 to 0.10 mm (0.003 to 0.004") thickness and may be suitable for some surface mount products, but this material is not recommended for fine-pitch applications. Few companies supply a dry film that is thin enough to meet fine-pitch criteria, but several suppliers can furnish liquid photo-imaged soldermask. Generally, soldermask openings should be 0.15 mm (0.006" greater in size than the land pattern feature. This allows a nominal 0.07 mm (0.003") clearance on all sides of the pads. Low-profile liquid photo-imaged soldermask is economical and commonly specified for surface mount applications, providing precise feature size and clearances.
ConclusionAssembly processing for fine-pitch, BGA and CSP can be refined to meet acceptable efficiency levels but bent leads and solder paste printing inconsistency often plague assembly process yields. And while using miniature fine-pitch devices has provided layout flexibility, the need to push components even closer together on very complex multilayer substrates may compromise testability and repair. BGA device use has provided higher assembly process yield and more layout flexibility, furnishing closer device spacing and shorter circuit paths between devices. Some companies are attempting to relieve area restrictions by integrating the function of several circuit functions into one or two multichip BGA devices. The customized or application-specific ICs may alleviate PCB gridlock but higher I/O and finer lead pitch generally will compel the designer to use more circuit layers on the PCB, thus increasing PCB fabrication complexity and cost.
Chip scale BGA packaging is seen by many as a viable answer to the space restrictions of newer generations of hand-held and portable electronics products. Companies also are expecting improved functionality as well as higher performance. When selecting the most efficient contact pitch for these devices, one must consider the silicon die size, the number of signal, power and ground contacts required, and the practical limitations when adapting these devices to the printed circuit structure. Although fine-pitch chip scale and chip size devices are considered an emerging technology, the major device suppliers and several leading electronics product manufacturers already have introduced or adapted a CSP variation of one type or another. This rapid growth in smaller package concepts was necessitated by the product developers' demand for reducing product size with increased functionality and, often, enhanced performance.
*µBGA is a registered trademark of Tessera.
VERN SOLBERG, senior applications engineer, may be contacted at Tessera, 3099 Orchard Dr., San Jose, CA 95134; (408) 894-0700; Fax: (408) 894-0285; E-mail: vern@tessera.com; Web site: www.tessera.com.