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New Solder Bumping Technology, Processes for 100 µm Pitch Flip-Chip Technology With Capillary Flow or No-Flow Underfill, Part I
September 7, 2010 |Estimated reading time: 12 minutes
AbstractIn this paper, the authors present new cost-efficient solder bumping and adapted assembly technologies for the processing of flip-chips with a pitch of 100 µm or less and solder ball diameters of 60 µm or 50 µm, respectively. The wafer bumping has been realized using a highly efficient Wafer Level Solder Sphere Transfer (WLSST) process. This technology uses a patterned vacuum plate in order to simultaneously pick up all of the preformed solder spheres, optically inspect for yield, and then transfer them to the wafer at once. This paper will discuss this technology and the process parameters for producing fine pitch solder bumps. The flip-chips were assembled on special BT- and FR4-material using reflow soldering. Due to the large thermal expansion mismatch between substrate and chip, special epoxy based underfill has to be used in order to increase the long term reliability of the lead-free solder joints. The use of capillary flow as well as of no flow underfill and applicable design rules for these highly miniaturized structures will be discussed. For cost efficiency reasons all processes investigated base upon standard processes of the surface mount technology, but are adapted to the requirements of highly miniaturized components. Results of the reliability tests will be discussed additionally. An analysis of the failure mechanism will be given and recommendations for further miniaturizations will be presented.IntroductionThe miniaturization of electronic packages is driven by a large variety of applications with high requirements on the level of integration and the form factor. This will be conducive to higher I/O-counts and a reduction of the pitch, which has an effect on the production systems as well. Due to size reduction and cost saving potential, flipchip-technology has gained importance in the field of highly miniaturized electronic devices. Specific bumping processes have been established in recent years. Common methods for applying solder onto the semiconductor wafer are for example stencil printing, electroplating, solder jetting and controlled collapse chip connection new process (C4NP) [1]. The most important requirements for bumping are a high yielded, fast and cost efficient process as well as, in many cases, low tooling costs.
Bumping Technology
The stencil printing process is still the technology of choice due to the economical advantages by using preexisting printing equipment in SMT production. With standard laser cut steel and nickel electroformed stencils peripheral arrays with 120 µm pitch can be printed at production level [2, 3] has shown the wafer level stencil printing for 60 µm pitch using special nano-coated stencils and type six and eight solder paste. With the nano-treatment of the side-walls and the bottom of the down to 20 µm thick stencils, the paste release from even very fine apertures can be improved.
The electroplating process is commonly used for high bump counts per wafer. The wafer is structured using a photolithographic process, which is followed by plating a copper mini bump on the bump sites. In a second photo patterning and plating process the solder alloy is applied and reflowed to form a sphere. With this technique, pitches down to 50 µm can be realized [4]. Due to the complex processes and mask manufacturing, the electroplating bumping technology is very expensive, especially for small wafer quantities.
Solder jetting is considered a very flexible bumping technology that is usable for three dimensional packaging, too. The process is flux-less and has additionally low thermal and mechanical stress input on the processed components. Solder ball diameters of down to 40 µm and a large variety of solder alloys can be used [5-6].
Very fine pitches down to 50 µm can be realized with the Controlled Collapse Chip Connection New Process (C4NP) which is described in [7-8]. According to a developed cost model, the C4NP process emerges lower cost compared to electroplating and stencil printing. The most critical cost factor of the C4NP process is the use of molds, since these impact directly the per wafer bumping costs.
All of the above mentioned bumping technologies require soldering or bonding technologies through conductive adhesives during assembly of the flip-chips. A new way for interconnects between component and substrate is described in [9]: The electrical connection is performed by the insertion of metallic pins in a ductile substrate material. With this special technology, a 30 µm pitch can be realized.
Flip-Chip Assembly
Besides the necessity of manufacturing very fine pitched bumps in order to cope with steady miniaturization, the production processes for assembling the flip-chips onto the substrates were improved as well. Circuitry structures that are eligible to the pitch of the dies were only realizable with thin film technology, which is very cost-intensive. Assembly machines used in high throughput production lines have to meet the needed placement accuracy as well and the vision systems have to detect the highly miniaturized bumps with high reliability.
Due to the heterogeneous material mix of the silicon die, the solder and the (anorganic) substrate material, a large CTE mismatch is inevitable. In order to absorb the thermal stress induced into the solder joints, underfill is used. The underfill technology can be divided into capillary flow and no flow processes. With capillary flow, the epoxy is applied after reflow soldering. The underfill flows underneath the die using the capillary effect. The flow rate and homogeneity of the underfill process is highly dependent on the gap size, the filler particle size, and the existence of residues of flux from the reflow process [10-11]. When using no flow underfill, a certain volume of the polymer based encapsulant is applied before flip-chip placement. After assembly, the solder is reflowed and the underfill cured during the same process [12-14].
Reliability Issues
One of the main reliability concerns in the flip-chip technology when using the highly miniaturized components on substrate level is the large mismatch of the coefficient of thermal expansion (CTE) between silicon die and printed circuit board. This thermal mismatch causes stress/strain in the solder joints. Various studies on solder joint reliability describe in detail simulation models and practical experiments. According to [15-16], the solder joint geometry has a highly significant influence on long term stability of the interconnections. Important parameters are the stand-off height and the contact angles of the solder joints on die and substrate side. To equalize the large thermal expansion mismatch, underfill materials is used in order to improve the reliability of the interconnections. Although some of the already mentioned influencing factors become less significant if underfill is applied, new possible influences appear, for instance the size of voids in the underfill [17]. In summary, the key factors that influence the long term reliability of the interconnections are named in [18]: The geometry of the solder joint, the underfill material, and the dimensions and the layout of the die.
As described in the paragraphs above, a large variety of solder bumping processes and assembly technologies have been established for the processing of flip-chips, of which each of the technologies has its own strength. In the following, this paper will present the technological enhancements of the Wafer Level Solder Sphere Transfer Technology (WLSST) for solder spheres of 60 µm and 50 µm in diameter and the assembly of test flip-chips on standard FR4- and BT-substrate materials using standard and modified SMT equipment and providing therefore a highly cost efficient process.
Aim and Processes UsedThe aim of the experimental study presented in this paper was the bumping of flip-chips with 100 µm pitch and solder spheres of 60 µm or 50 µm, respectively, in diameter, the structuring of FR4- and BT-substrates with the necessary fine pitch structures, and the assembly of the dies using standard production equipment. This makes the process chain from wafer bumping to flip-chip assembly very cost efficient and flexible.
Wafer Bumping Process
The wafer bumping has been realized using the highly efficient and flexible wafer level solder sphere transfer process, also known as gang ball placement, that is described in detail in [1,19]. The WLSST tool can integrate several of the most necessary operations when depositing solder volumes on wafer level, like flux coating, solder reflow, inspection and rework processes, but can be configured to expand and complement the existing equipment and processes in the fab.
The main process steps of the bumping technology are shown in Figure 1. Characteristic for this process is that all preformed solder spheres needed for one wafer are transferred to the wafer in one single process step. This is realized with a patterned vacuum stencil with openings corresponding to the under bump metallization on the wafer. The tool is placed over and lowered down to the sphere reservoir (a). Next vacuum is applied to selectively pick up the solder spheres. After inspection for missing (b) and extra (c) spheres the tool is aligned to the wafer. By lowering the stencil to the wafer the solder spheres are brought in contact with the wafer (d) on which flux has been pre applied. The process ends with turning off the vacuum and raising the tool (e) and reflow of the solder spheres (f). As yet with this technology it was possible to place solder spheres of 80 µm in size with high yields. For the research on the placement of 60 µm and 50 µm solder spheres the process in principle was not modified since the placement accuracy for tool to wafer of 15 µm is sufficient. By this the equipment can be still considered a standard process for wafer bumping.Figure 1: Process for wafer level solder sphere transfer technology.
Stencils used in the WLSST technology can be manufactured similar to tools used for stencil printing technology. But for the placement of 60 µm and 50 µm predominantly the stencil quality had to be improved to secure sphere pick up and release. Laser cut stencils were compared to nickel plated ones regarding dimensional accuracy and achievable yield. The experiments showed that for high I/O-counts nickel plated stencils showed a better performance. The size of the openings should be slightly smaller than the size of the solder spheres. In case of the 60 µm solder spheres the openings had a size of 40 µm*40 µm. However, stencil thickness has only little influence on the process.Figure 2: Chip with 60 micron solder spheres at the first row.The important parameters of the flip-chips used for the processability study presented in this paper are given in table 1. The silicon die has a thickness of 0.8 mm and an edge length of 10 mm. The preformed solder spheres are made of a SnAgCu alloy and are placed on a NiAu UBM realized in an electroless nickel process. Four rows of bumps have been realised at each side of the die, each with a different passivation opening for solder spheres measuring between 60 µm (first row) and 30 µm (fourth row) (figure 2). The I/O-count is dependent on the solder sphere size - for example 376 I/Os for 60 µm spheres, 368 I/Os for 50 µm spheres. 277 dies are placed on one wafer making it per wafer 104,152 I/Os or 101,936 I/Os, respectively for 60 µm spheres or 50 µm spheres, respectively. To detect failures during the reliability tests each die has a daisy chain structure. Table 1: Parameters of the flip-chip.Layout and Substrate Structuring
It was the aim for the substrate structuring that standard and low cost processes can be used. The properties of the employed substrate materials are shown in table 2. The thickness of both materials is 0.8 mm. The coefficients of thermal expansion are nearly the same, whereas the glass transition temperatures varies about 30 K. The copper metallisation has a thickness of 9 µm at the beginning of the structuring process. After structuring and application of the solder mask, a NiAu surface finish was applied to the copper circuitry.Table 2: Properties of the substrate materials.The layout of the used test coupons is shown in figure 3. A number of six flip-chips can be assembled onto the substrate, whereas the structures of the flip-chip and the test coupon are realized in a way that only one layout is used for both, the dies with 60 µm and 50 µm spheres. Again, a daisy chain connection is integrated for each of the flip-chips and each chip can be connected for online measuring during reliability testing.Figure 3: Layouts of the test coupons.The specification for the structures on the test coupon in terms of fineness were 40 µm lines and 50 µm spaces for the 50 µm solder spheres and 50 µm lines and 40 µm spaces for the 60 µm solder spheres. Additionally, two different foot prints were realized: One conventional design (V3.3 and V3.3/1) and one teardrop-design (V3.2) (figure 3), whereas V3.3/1 is an improved version of V3.3 concerning solder mask registration. A preliminary test showed a very good wetting of the solder spheres on the land pads. Therefore, against usual procedure, ultra fine pitch solder mask defined pads were realized as well on the test coupons.Figure 4: Investigated assembly processes: Capillary Flow Underfill (left) and No Flow Underfill (right).Table 3: Parameters of the assembly process.Assembly Process and Reliability Testing
The processes used for the assembly of the components on the test coupons were carried out on standard production equipment (table 3). Two separated process chains were investigated for the assembly of the flip-chip with 60 µm and 50 µm solder bumps (see figure 4). One was the classic process with capillary flow underfill. Flux was applied to the substrate right before component placement. After forced convection reflow soldering, the underfill was dispensed in L-shape. Two different underfills were in use. Throughout all process steps the test coupons were attached to a work piece carrier in order to minimize the bending of the substrates during die placement and reflow soldering. The second process investigated is the use of no flow underfill. Before component placement a defined amount of underfill was dispensed Dot- or X-Shape, respectively. Two no flow underfills have been used. Subsequently, the die was assembled with varying placement velocities, placement forces and holding times after placement. During reflow soldering the solder wets the land pads and the underfill cures. A work piece carrier has been used during this process chain as well.Table 4: Test program for assembly tests (capillary flow underfill).For the experiments with capillary flow underfill, the combination of solder sphere size, passivation opening and footprint diameter has been varied in several iterations.
In the first version the passivation opening and the footprint were of the same size. For experiments number 2 and 3 the 60 µm solder spheres were placed on the 2nd bump row during wafer bumping (see figure 2) to increase the stand-off after reflow soldering and therefore increasing the long term reliability of the solder joints. The difference lies in the PCB layout, since V3.3/1 is an improved version of V3.3. For experiments 1 to 3 underfill B has been used. In version 4 and 5 the passivation opening and the footprint were of the same size. Aim of this experiment was the comparison of the reliability of the solder joints formed of 60 µm or 50 µm solder spheres, respectively. Experiments 4 and 5 were carried out using underfill A.
Table 5: Test methods for reliability testing (capillary flow underfill).Different methods of reliability tests have been carried out with the test coupons (table 5). The test coupons from experiments 1 to 3 were tested according to MILSTD883G, Method 1010.7, Condition B (-55 °C/ +125 °C). Humidity testing was carried out as well according to EIA/JESD22-A101-B. The specimen of experiments 4 and 5 were stressed 1,000 cycles -40 °C/ +125 °C according to DIN EN 60 068-2-14. All specimens were connected to an online measuring system in order to determine the exact cycle of the first failure.Figure 5: Measurement of height and diameter of 60 µm and 50 µm solder spheres, respectively.Editor's Note: Be sure to check out next week's Tech Tuesday Newsletter for the conclusion of this paper.