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Trouble in your Tank: Optimizing the Liquid Photoimageable Soldermask Process, Part 1
Introduction
Some of my recent columns in have focused on identifying and resolving some very specific technical issues related to soldermask. It would be prudent at this time to present information on the soldermask process itself in hopes of preventing defects in the future. But first, one should understand the key requirements for the soldermask, in particular for today’s lead-free assembly requirements and fine-pitch circuitry.
The Requirements
Increased wiring density is driving soldermask performance to levels never seen before. Requirements to hold 2 and 3 mil dams are commonplace, especially with the increased use of HDI technology. In addition, PCB end-users are requiring the soldermask to display higher electrical and environmental properties as well as perform effectively with the myriad of lead-free solderable finishes (ENIG, Selective ENIG-OSP, ENEPIG, lead-free HASL, immersion silver and immersion tin).
Soldermask is applied after the surface traces are formed. The challenge for these materials is to impart electrical properties where, historically, soldermask was not part of electrical design. Soldermask attributes are shown in Table 1. (Source: IPC Technology Roadmap 2013)
Editor's Note: This article originally appeared in the May 2013 issue of The PCB Magazine.
