Cadence’s Brad Griffin Digs Deep Into DDR

Estimated reading time: 12 minutes

KD: Excellent. Let's talk about serial interfaces. Tell us where they’ve come from and where we’re going with them.

BG:  One of the most interesting things in signal integrity is around the serial interfaces and it also sort of mixes with memory interface design as well, which is a parallel bus. With serial interfaces, the way that we typically check compliance on them is by running many signals which we call high-capacity simulation, and by many I mean like millions and tens of millions of bits. We're looking to see how many of those bits actually get transferred correctly. So when you go to the PCI-SIG, the special-interest group, they have a bit-error rate test that they do with hardware. Well we can do the same sort of bit error rate testing with software. Our signal integrity software supports a high-capacity simulation and then lets you look at the eye diagram and just like with PCI-SIG we have that compliance test built into our software.

There are a couple of really interesting things about what's happening in this space. One is the most popular serial interface by far, which is PCI Express. We’ve been at PCIe 3.0 for a few years now, and that’s an 8 Gb/s interface. Most people here at DesignCon are talking about up to 28 or 56 Gb/s, so 8 is a little bit behind the bleeding edge at this point. But what's going to be happening this year is PCI-SIG is going to approve the 4.0 spec, which is moving it to 16. Still maybe not on the bleeding edge, but doubling the data rate is very significant. Here’s one of the cool things we’re showing in our booth: If someone who is using 8 Gb/s today wants to see if their same hardware will support a 16 Gb/s data transfer, we can help them check that feasibility. It’s really quite interesting because you can see by default the answer is probably no, the eye is going to be closed and you’re not going to meet your bit error rate testing. But because these transceivers and receivers have such advanced equalization in them we have what's called algorithmic models that sit on both sides, transmitter and receiver, and this is the same type of stuff we’re going to see in devices that come out and support PCIe 4.0. We can turn on a level of equalization and see if when we boost that signal if we can open up that eye and see if it’s going to meet those compliance requirements that are going to be associated with doubling the date rate from 8 to 16.

That's a pretty interesting thing that's going to be happening in 2015. And when we talked about LPDDR4, that data rate is actually going to go as high as 4266, so that's going to be working in a similar way that serial links were working about two or three years ago. The same equalization that you needed in serial links a few years ago are going to be needed in memory interfaces this year. We will support that with our algorithmic modeling interface. Today we can show AMI modeling associated with DDR4 and LPDDR4 as well as, of course, serial links. It’s just tremendously exciting that, with all this different technology, we get data passed across the ether into the cloud as fast as possible. All this stuff is really exciting, and the fact that we’re able to analyze this and help customers get to market right the first time is what we're really excited about at Cadence, and the Allegro technology is providing that link to getting the product done right the first time. 

KD: Thanks for taking the time to talk with me today, Brad.

BG: Thank you, Kelly.

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