Global Citizenship: Cultivating Cross-border Partnerships With Integrity
Nolan’s Notes: Moving Forward With Confidence
The Knowledge Base: Beyond the Badge—Why Membership Matters More Than Ever
The War on Soldering Defects under Area Array Packages: Head-in-Pillow and Non-Wet Open
August 17, 2015 | Jason Fullerton, AlphaEstimated reading time: 2 minutes
The most difficult aspect of any soldering defect on an area array package is the inability to observe the defect easily. It is important to understand the characteristics of soldering defects in order to identify the proper action to take to mitigate the defects in a soldering process.
Head-in-pillow (HiP) defects are soldering defects on area array packages characterized by a lack of coalescence between the solder paste deposit and the package solder bump. In these defects, the solder paste deposit coalesces properly with itself and typically wets to the PCB land. Displacement of each solder deposit (paste and bump) is a common feature of HiP defects.
Non-wet open (NWO) defects are soldering defects characterized by a lack of wetting to a PCB land by a fully coalesced solder deposit on an area array package. In this defect, the solder paste and the package solder bump coalesce together fully without wetting to the PCB land.
A spherical or nearly spherical shape along the PCB side of the bump is a common feature of NWO defects.
What Head-in-Pillow and Non-Wet Open are not
It is important to discuss defects that can share some symptoms with HiP and NWO, in order to contrast against defects that require different mitigation actions. One example of a defect with similar symptoms to HiP and NWO is insufficient solder paste volume transfer during printing. In this case, it can appear that no wetting has occurred to the land and mimic NWO (especially if no paste has been transferred). If a small amount of paste has been printed, the resulting connection can initially appear to be consistent with HiP. Troubleshooting of HiP and NWO defects should include steps to ensure the solder paste printing process is properly controlled and performing well.
Another defect that can be confused with HiP is cold solder, which is characterized by a lack of coalescence of the solder paste deposit. HiP is a defect that occurs in the presence of a well-defined and controlled reflow process, which ensures coalescence of the solder paste deposit. Diagnosis of a defect as HiP should include an examination of the reflow profile to ensure that the process is not at risk of causing the occurrence of cold solder.
Non-wetting to a PCB land has many causes that should be familiar to most with experience troubleshooting solder defects. These defects can easily be confused with NWO since both defects share a symptom: poor wetting of a coalesced solder bump to the PCB land. The key difference is that NWO defects result in a solder bump that is spherical along the PCB side. A defect that is solely caused by poor PCB solderability will generally demonstrate the same shape as a typical area array solder connection: flatter and wider than a sphere and generally sharing the contour of the land along that interface. Testing the solderability of the PCB lands is an important step when attempting to determine if a wetting defect is a result of NWO defects.
Editor's Note: This article originally appeared in the August 2015 issue of SMT Magazine.
Share on:
Suggested Items
Preventing Surface Prep Defects and Ensuring Reliability
06/10/2025 | Marcy LaRont, PCB007 MagazineIn printed circuit board (PCB) fabrication, surface preparation is a critical process that ensures strong adhesion, reliable plating, and long-term product performance. Without proper surface treatment, manufacturers may encounter defects such as delamination, poor solder mask adhesion, and plating failures. This article examines key surface preparation techniques, common defects resulting from improper processes, and real-world case studies that illustrate best practices.
Breaking Silos with Intelligence: Connectivity of Component-level Data Across the SMT Line
06/09/2025 | Dr. Eyal Weiss, CybordAs the complexity and demands of electronics manufacturing continue to rise, the smart factory is no longer a distant vision; it has become a necessity. While machine connectivity and line-level data integration have gained traction in recent years, one of the most overlooked opportunities lies in the component itself. Specifically, in the data captured just milliseconds before a component is placed onto the PCB, which often goes unexamined and is permanently lost once reflow begins.
BEST Inc. Introduces StikNPeel Rework Stencil for Fast, Simple and Reliable Solder Paste Printing
06/02/2025 | BEST Inc.BEST Inc., a leader in electronic component rework services, training, and products is pleased to introduce StikNPeel™ rework stencils. This innovative product is designed for printing solder paste for placement of gull wing devices such as quad flat packs (QFPs) or bottom terminated components.
See TopLine’s Next Gen Braided Solder Column Technology at SPACE TECH EXPO 2025
05/28/2025 | TopLineAerospace and Defense applications in demanding environments have a solution now in TopLine’s Braided Solder Columns, which can withstand the rigors of deep space cold and cryogenic environments.
INEMI Interim Report: Interconnection Modeling and Simulation Results for Low-Temp Materials in First-Level Interconnect
05/30/2025 | iNEMIOne of the greatest challenges of integrating different types of silicon, memory, and other extended processing units (XPUs) in a single package is in attaching these various types of chips in a reliable way.