Atomically Flat Tunnel Transistor Overcomes Fundamental Power Challenge of Electronics

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The TFET designed by the UCSB team overcame this challenge in a few ways, most significant being the use of a layered two-dimensional (2D) material called molybdenum disulphide (MoS¬2). As the current-carrying channel placed over a highly doped germanium (Ge) as the source electrode, MoS2 offers an ideal surface and thickness of only 1.3nm. The resulting vertical heterostructure provides a unique source-channel junction that is strain-free, has a low barrier for current-carrying electrons to tunnel through from Ge to MoS¬2 through an ultra-thin (~0.34nm) van der Waals gap, and a large tunneling area.

"The crux of our idea is to combine 3D and 2D materials in a unique heterostructure, to achieve the best of both worlds. The matured doping technology of 3D structures is married to the ultra-thin nature and pristine interfaces of 2D layers to obtain an efficient quantum-mechanical tunneling barrier, which can be easily tuned by the gate," commented Deblina Sarkar, lead author of the paper and PhD student in Banerjee's lab.

"We have engineered what is, at present, the thinnest-channel subthermionic transistor ever made," said Banerjee. Their atomically-thin and layered semiconducting channel tunnel FET (or ATLAS-TFET) is the only planar architecture TFET to achieve subthermionic subthreshold swing (~30 millivolts/decade at room temperature) over four decades of drain current, and the only one in any architecture to achieve so at an ultra-low drain-source voltage of 0.1V.

Ajayan, co-author and professor of chemical and biomolecular engineering at Rice University, commented, "This is a remarkable example showing the uniqueness of 2D atomic layered materials that enables device performance which conventional materials will not be able to achieve. This is perhaps the first breakthrough in a series of novel devices that people will now aspire to build using 2D materials."

"The work is a significant step forward in the search for a low voltage logic transistor. The demonstration of sub-thermal operation over four orders of magnitude is impressive, and the on-current also advances the state-of-the-art. There is still a long ways to go, but this work demonstrates the potential of 2D materials to realize the long-sought, low-voltage device," commented Mark Lundstrom, professor of electrical and computer engineering at Purdue University.

"We have demonstrated how to achieve the most important metric of steep subthreshold swing that meets ITRS requirements. Our transistor can be utilized for a number of low-power applications including arenas where the steep subthreshold swing is the main requirement, such as biosensors or gas sensors. With improved performance, the range of applications of this transistor can be further expanded," explained Wei Cao, a PhD student in Banerjee's group and a co-author of the article.

"This work represents an important step of bringing 2D materials closer to real applications in electronics. The use of 2D materials in tunneling transistors started only recently, and this paper gives the whole field yet another strong boost in improving the characteristics of such devices even further," commented Dr. Konstantin Novoselov, a professor of physics at University of Manchester. Novoselov was co-recipient of the 2010 Nobel Prize in Physics, awarded for the discovery of graphene.

"When I first heard Banerjee's idea of using 2D materials for designing inter-band tunneling transistors in 2012, I recognized its merit and immense potential for ultra-low power electronics. I am pleased to see that his vision has been realized," commented James Hwang, professor of electrical engineering at Lehigh University, who was then the AFOSR program manager responsible for funding this research.

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