Design for Test in the U.S. Market
March 17, 2016 | W. Scott Fillebrown, LIBRA INDUSTRIES INC.Estimated reading time: 1 minute

With most high-volume printed circuit assembly being sent outside the United States, we have a unique challenge for testing the lower volume/high turnover assemblies domestically. However, with a little planning and the right contract manufacturer (CM), test does not need to be an issue.
Here is the challenge: The U.S. market mainly is comprised of higher technology/lower production quantity assemblies. In many cases, incircuit bed of nails testing is not an option due to development time and cost, not to mention the difficulty associated with finding a place for 30–40 mil test points. These same test points also create significant EMI concerns for most electrical engineers. The challenge is to find a way to thoroughly test a fully populated circuit in a timely, cost-effective way, without compromising signal integrity.
Depending on the technology, the challenge can be as simple as making minor design changes, which actually can happen at the Ger ber level versus requiring a significant revision to the board in question. First let’s conquer the simple. For analog, RF, and lower technology digital boards, the approach is the simplest. Typically, straightforward flying probe test is the answer. The better EMS companies use a dual-sided flying probe tester as shown in Figure 1. For this test approach, the test engineer simply asks that the vias not be covered with soldermask, which can be a simple change handled at the CAM/Gerber level. Because flying probe testers can generally test a via with a 20 mil pad and a 10 mil hole, the holes do not need to be plated shut. Depending on the test coverage, the test department may recommend adding vias, assuming the design can handle it from an electrical perspective.
Editor’s Note: This article originally appeared in the March 2016 issue of The PCB Magazine.
Suggested Items
Nordson Electronics Solutions Develops Panel-level Packaging Solution for Powertech Technology, Inc. That Achieves Yields Greater Than 99% for Underfilling During Semiconductor Manufacturing
06/11/2025 | Nordson Electronics SolutionsNordson Electronics Solutions, a global leader in reliable electronics manufacturing technologies, has developed several solutions for panel-level packaging (PLP) during semiconductor manufacturing. In one particular case, Nordson’s customer, Powertech Technology, Inc. (PTI) saw underfill yields improve to greater than 99% as they plan to transition from wafers to panels in their manufacturing operations. edwd
DuPont/Qnity Innovators in Semiconductor Materials Named 2025 Heroes of Chemistry
06/10/2025 | DuPontDuPont today announced that 13 of its current and former scientists and engineers have been named 2025 Heroes of Chemistry by the American Chemical Society (ACS) for an innovative program that progressed semiconductor lithography.
Zhen Ding Promotes Digital Transformation and Embraces AI Business Opportunities
06/06/2025 | Zhen Ding TechnologyOn May 27, 2025, General Manager Chen-Fu Chien of Zhen Ding Technology Group was invited to attend the "2025 Two Thousand Forum" held by The CommonWealth Magazine.
Leidos Using Quantum Technology to Thwart GPS Jamming
06/05/2025 | PRNewswireSusceptibility to jamming is a significant military vulnerability of the Global Positioning System (GPS) signal. Through a Defense Innovation Unit contract, Leidos is developing an alternative navigation technology that measures variations in the Earth's magnetic field and harnesses the quantum properties of nitrogen in diamonds.
Growing Demand for Mid-Size Displays Opens New Opportunities for FMM-Free OLED Technologies
06/05/2025 | TrendForceTrendForce’s latest report on the display industry reveals that OLED technology—valued for its self-emissive structure, high contrast ratio, and lightweight design—continues to expand its market presence, primarily in small-size applications such as smartphones.