-
- News
- Books
Featured Books
- pcb007 Magazine
Latest Issues
Current IssueThe Essential Guide to Surface Finishes
We go back to basics this month with a recount of a little history, and look forward to addressing the many challenges that high density, high frequency, adhesion, SI, and corrosion concerns for harsh environments bring to the fore. We compare and contrast surface finishes by type and application, take a hard look at the many iterations of gold plating, and address palladium as a surface finish.
It's Show Time!
In this month’s issue of PCB007 Magazine we reimagine the possibilities featuring stories all about IPC APEX EXPO 2025—covering what to look forward to, and what you don’t want to miss.
Fueling the Workforce Pipeline
We take a hard look at fueling the workforce pipeline, specifically at the early introduction of manufacturing concepts and business to young people in this issue of PCB007 Magazine.
- Articles
- Columns
Search Console
- Links
- Media kit
||| MENU - pcb007 Magazine
Happy’s Essential Skills: Failure Modes and Effects Analysis (FMEA)
April 6, 2016 | Happy HoldenEstimated reading time: 12 minutes
Figure 2: FMEA flow chart.
Steps in Performing FMEA
- Discuss and define system functional requirements (scope), including all modes of operation (list in order of decreasing importance). Is it for concept, system, design, process, product or service and customer needs?
- Develop a functional block diagram and a reliability block diagram (Figure 2) for each subassembly being analyzed.
- Define parameters and functions of each functional block required for successful operation of the system.
- Using the FMEA forms to document the further steps, identify potential failure modes for each of the functional blocks.
- Analyze system or subassembly functions affected by factors such as those in the list of FMEA considerations.
- Identify all possible causes for each failure mode of the functional block being analyzed. The causes must be detailed to the component level wherever possible. These are potential failure modes. If necessary, go back and rewrite the function with more detail to be sure the failure modes show a loss of that function.
- Identify all possible ways the failure modes could affect the functions of the higher level assemblies.
- Assign the frequency, criticality, and detection values for each failure mode. (Tables 1– 3)
- Obtain the RPN by multiplying the three values assigned in step 8. This priority number will allow us to focus on the most important failure modes first.
- Determine all the possible root causes and corrective actions for each failure mode, and update the design status as it progresses.
- Summarize the failure modes and corrective actions in order of decreasing RPN.
- Focus on eliminating at least the 50% of the failure modes with the highest RPN.
An example of a FMEA analysis is shown in Figure 3.
Page 3 of 5
Suggested Items
Bridging the Gap Between PCB Designers and Fabricators
04/03/2025 | Stephen V. Chavez, Siemens EDAWith today’s advanced EDA tools, designing complex PCBs in the virtual world does not necessarily mean they can be built in the real world. This makes the relationship between a PCB designer and a fabricator pivotal to the success of a project. In keeping with solid design for manufacturing (DFM) practices, clear and frequent communication is needed to dial and lock in design constraints that meet expectations while addressing manufacturing concerns.
IPC APEX EXPO Newcomer: Faith DeSaulnier of TTM Technologies
04/03/2025 | I-Connect007 Editorial TeamDuring the Newcomer’s Welcome Reception at IPC APEX EXPO, the I-Connect Editorial Team spoke with several first-time attendees. The following is our interview with Faith DeSaulnier, a process engineer based at TTM Technologies’ facility in Forest Grove, Oregon.
Ansys Semiconductor Solutions Certified by TSMC for Reliable, Accurate Analysis of Evolving Chip Designs
04/03/2025 | PRNewswireAnsys announced that PathFinder-SC is certified as a new ESD analysis solution for customers designing with TSMC's N2 silicon process technology. PathFinder-SC delivers a novel verification solution that provides superior capacity and performance, easily accommodating large designs in the cloud.
Real Time with... IPC APEX EXPO 2025: Insights into PCB Design and Manufacturing with Polar Instruments
04/03/2025 | Real Time with...IPC APEX EXPOErik Bateham discusses Polar's latest book, which enhances insights for PCB designers and manufacturers. The book, "The Designer's Guide to... More Secrets of High-Speed PCBs," features a guest chapter on 2D via design modeling. Erik highlights the industry's shift towards UHDI and the challenges in measuring at micron levels.
Connect the Dots: Stop Killing Your Yield—The Hidden Cost of Design Oversights
04/03/2025 | Matt Stevenson -- Column: Connect the DotsI’ve been in this industry long enough to recognize red flags in PCB designs. When designers send over PCBs that look great on the computer screen but have hidden flaws, it can lead to manufacturing problems. I have seen this happen too often: manufacturing delays, yield losses, and designers asking, “Why didn’t anyone tell me sooner?” Here’s the thing: Minor design improvements can greatly impact manufacturing yield, and design oversights can lead to expensive bottlenecks. Here’s how to find the hidden flaws in a design and avoid disaster.