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Copper Pillar Plating Systems: High Speed, Low Heat
November 1, 2018 | E. Walch, DJ., C. Rietmann, Ph.D., and A. Angstenberger, Ph.D.Estimated reading time: 1 minute
Abstract
The industry is seeing ever-more stringent requirements of interconnect technologies (ICT) from die through final assembly, in particular digital and analog high frequencies, undistorted signal propagation and efficient heat propagation are concerned. From wafer level packaging to the finished printed circuit board, copper pillars, and solid copper posts (with printed circuitry it is copper filled through-holes, respectively) continue to play a vital role in coping with high-speed/high-frequency and high wattage of sub and final assemblies.
Commonly used packaging concepts comprising wafer level plating, through-silicon-vias (TSV), redistribution layer design (RDL), intermediate pillars, macrobumps and copper-filled through-holes in the final circuitry will be addressed in this article, followed by an overlook of the extremely different pillar geometries within each packaging level, posing individual challenges on the copper plating chemistry and process. Practical aspects, namely dialing in the chemistry additives and process windows to match the relevant applications‘ needs will be reported, as well as the ongoing R&D work targeted for current and future requirements. The article concludes with actual research results on achievable copper textures and the subsequent performance of the plated copper interconnects as far as crystal lattices and the related thermal reliability are concerned.
To read the full version of this article which originally appeared in the September 2018 issue of PCB007 magazine, click here.
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