Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications
December 10, 2019 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Global Unichip Corporation (GUC) successfully deployed the Cadence® digital implementation and signoff flow and delivered advanced-node (N16, N12 and N7) designs for artificial intelligence (AI) and high-performance computing (HPC) applications. Through use of the Cadence Innovus™ Implementation System and the Voltus™ IC Power Integrity Solution, GUC achieved first-pass silicon success and met its GHz performance target for its multi-billion gate designs.
Traditional digital implementation and signoff tools lack the capacity GUC required for their multi-billion gate designs during the implementation and signoff stages. Alternative solutions on the market must be greatly scripted because they don’t offer a shared data model-level integration, requiring more manual work with increased design margins and limited performance. Where the traditional tools fall short, the tightly integrated Cadence solution helped GUC meet power, performance and area (PPA) targets and deliver their large-capacity, advanced designs on time.
The Innovus Implementation System improved the GUC design team’s productivity through its efficient hierarchical partitioning flow, advanced top-level floorplanning and block implementation and closure capabilities. The Voltus IC Power Integrity Solution enabled GUC to accurately analyze the top-level full-chip static/dynamic power, IR drop and electro-migration through its distributed processing capability using innovative extensive parallelism technology. The seamless shared data model-level integration between the Cadence tools provides GUC with an efficient way to close signoff EM-IR issues during block implementation, reducing costly iterations and engineering change orders (ECOs).
“As a leader in ASIC design, we need to deliver highly complex designs to customers quickly, particularly for emerging application areas like AI and HPC,” said Louis Lin, senior vice president of Design Services at GUC. “Through our deep collaboration with Cadence, we deployed their digital implementation and signoff tools quickly and easily, and the Cadence team also provided prompt support to further optimize our delivery cycle time and achieve our PPA targets.”
The Cadence Innovus Implementation System and Voltus IC Power Integrity Solution are part of the broader digital implementation and signoff full flow and provide customers with a faster path to design closure. The tools in the flow support the company’s Intelligent System Design™ strategy, enabling advanced-node system-on-chip (SoC) design excellence for AI and HPC applications.
Suggested Items
I-Connect007 Editor’s Choice: Five Must-Reads for the Week
05/09/2025 | Andy Shaughnessy, Design007 MagazineTrade show season is wrapping up as we head into summer. Where has the time gone? I hope you all get the chance to take a vacation this year, because I know you’ve earned one. Speaking of which, when was my last vacay? If I can’t remember, it’s probably time for one. It’s been a busy week in electronics, with fallout from the back-and-forth on tariffs taking up most of the oxygen in the room. We have quite an assortment of articles and columns for you in this installment of Must-Reads. See you next time.
Imec Coordinates EU Chips Design Platform
05/09/2025 | ImecA consortium of 12 European partners, coordinated by imec, has been selected in the framework of the European Chips Act to develop the EU Chips Design Platform.
New Issue of Design007 Magazine: Are Your Data Packages Less Than Ideal?
05/09/2025 | I-Connect007 Editorial TeamWhy is it so difficult to create the ideal data package? Many of these simple errors can be alleviated by paying attention to detail—and knowing what issues to look out for. So, this month, our experts weigh in on the best practices for creating the ideal data package for your design.
RF PCB Design Tips and Tricks
05/08/2025 | Cherie Litson, EPTAC MIT CID/CID+There are many great books, videos, and information online about designing PCBs for RF circuits. A few of my favorite RF sources are Hans Rosenberg, Stephen Chavez, and Rick Hartley, but there are many more. These PCB design engineers have a very good perspective on what it takes to take an RF design from schematic concept to PCB layout.
Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems
05/08/2025 | Cadence Design SystemsAt its annual flagship user event, CadenceLIVE Silicon Valley 2025, Cadence announced a major expansion of its Cadence® Millennium™ Enterprise Platform with the introduction of the new Millennium M2000 Supercomputer featuring NVIDIA Blackwell systems, which delivers AI-accelerated simulation at unprecedented speed and scale across engineering and drug design workloads.