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Book Excerpt: 'The Electronics Industry’s Guide to… The Evolving PCB NPI', Chapter 3
January 4, 2023 | I-Connect007 Editorial TeamEstimated reading time: 2 minutes
Chapter 3: Streamlining Data Preparation
With the need to move design data efficiently into manufacturing for assembly and test purposes, starting from a single source of intelligent data seems to be obvious. However, with different applications with different capabilities this can be difficult to achieve. Real-world support for any format can vary between machine and software vendors. The optimal goal should be to create a single digital twin of the product upfront regardless of the downstream applications that need that data.
If we consider the PCB and the parts being placed on it, their data should have significant commonality across the many steps in PCB assembly and test. Typically, we find that process and test engineers think there is much more machine-specific data across their lines than there really is in practice.
Solutions exist in the market that can manage this common data and then deliver machine-specific information to the machine software as needed, on demand. In this way, the factory can maintain the common data, but, more importantly, they have a common part library data that is independent of the line. Remember when we talked about the move from mixed vendor lines to single vendor lines and mixed-line factories? The ability to manage part data in this context is key to efficiently streamlining the NPI phase.
First, let’s start with the typical data preparation tasks that form the base for a typical NPI flow. Being able to accurately import the source layout CAD data is an important first step. As we discussed in chapter one, ODB++ and IPC 2581 provide a common, standardized data format for layout information. However, not all CAD data is the same, even in the context of one format such as ODB++. This is because different designers use unique conventions in their source libraries. The position and rotation of each component placement can be inconsistent for any single format because each component location is based on the definition of the library cell that it references. Why does this decrease efficiency?
Consider that, during the SMT process, the machine picks a component up from a feeder and positions that component, rotating it before releasing it on the board. What the machine considers for the rotation is based on its perspective and the orientation of the part in the feeder. However, what the design software considers for position and orientation is based on an arbitrarily defined cell library. The variations in that cell library are a result of the environment that the designer works in. What is the origin of the cell? Is it pin 1? Is it the middle of the part? Is it a corner on the cell? What is the rotation of the part at 0 degrees? Is it pin 1 to the left or to the right? What about IC components with many pins? Is pin 1 in the lower right corner, or maybe the lower left?
See Figure 3.1 for how a designer may have defined their source footprint, which is what is used for placement position and angle. We have a polarized part here but pin 2 is associated with the silkscreen indicator.
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