GUC Delivers its First TSMC N3 Chip, AI-Optimized N5 Design Using Cadence Digital Solutions

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Cadence Design Systems, Inc. announced that Global Unichip Corp. (GUC) successfully delivered an advanced HPC design and a CPU design using Cadence® digital solutions. The HPC design was created using the Cadence Innovus™ Implementation System on TSMC’s advanced N3 process and featured a 3.5 million instance count that reached clock speeds of up to 3.16GHz. The CPU design was created using the AI-enabled Cadence Cerebrus™ Intelligent Chip Explorer and the digital full flow on the TSMC N5 process technology, delivering 8% reduced power and a 9% area improvement while significantly improving engineering productivity.

The Innovus Implementation System’s highly accurate GigaPlace engine provided GUC with support for TSMC FinFlex™ cell row placement and consideration for pin access throughout the flow for N3 design rule checking (DRC) closure. The state-of-the-art GigaOpt engine delivered improved optimization by enabling the most optimal configuration from the TSMC N3 library while balancing different cell row utilization. The Innovus Implementation System also includes a massively parallel architecture and incorporates the well-established NanoRoute engine, which enabled GUC to address signal integrity early in the design flow while improving post-route correlation.

Cadence Cerebrus, coupled with the Cadence digital flow, was instrumental in providing GUC with power, performance and area (PPA) benefits as well as the ability to perform synthesis through implementation and signoff on their 5nm CPU design, optimizing engineering team productivity. Unique to Cadence Cerebrus is its reinforcement learning engine that autonomously optimized GUC’s design flow, allowing the team to exceed human engineering potential and accelerate time to market.

“GUC is a market leader providing advanced chip solutions for AI, HPC, 5G, industrial and other emerging applications,” said Dr. Louis Lin, senior vice president of Design Services at GUC. “Given our commitment to deliver the most competitive designs to our customers, it is important for us to invest in leading-edge technologies. The Cadence Cerebrus Intelligent Chip Explorer, in conjunction with the broader digital flow, was the natural choice to help us achieve faster design turnaround via AI technology while also improving PPA. The Innovus Implementation System was instrumental in helping us deliver our first N3 chip, enabling our team to accelerate the creation of our high-performance, low-power HPC design.”