Transfer Efficiencies in Stencil Printing

Estimated reading time: 6 minutes

By Grant Burkhalter, Esse Leak, Chrys Shea, Ron Tripp, and Greg Wade, ALPHA

The goal of stencil printing is to deposit the proper amount of solder paste in the proper location. While this is simple, many factors influence the process. And although these factors are well known, they are not always easy to control. Even when the best way to deposit the proper amount of paste robustly is known, it may not be possible. PCB designs often combine fine-feature devices that require thinner stencils with thru-hole connectors or RF shields that require thicker stencils, leaving the assembler with a dilemma - how to ensure the proper amount of paste for each device. Research on how the stencil itself influences the printing process began in 2001 with a print-optimization study that examined the effects of aperture size, shape, degree of taper, and electropolish on solder paste release.1 This release was measured as transfer efficiency, which is calculated as the volume of paste actually deposited divided by the volume of the stencil aperture, expressed as a percent (Figure 1).

TE=100 × (2.535 × AR 3.426), whereTE represents transfer efficiency andAR represents area ratio.

This study quantified the mechanics of stencil release, and subsequent analysis of more than 10 million data points revealed information about manufacturing techniques, including a high dependence of transfer efficiency on the area ratio of the stencil aperture itself. Area ratio is defined as the area of the circuit-side opening of the stencil, divided by the area of the aperture walls. Statistical analysis shows that, for given solder paste and print parameters, 95% of transfer efficiency depends on area ratio. As the area ratio increases, the standard deviation of transfer efficiency decreases, resulting in more repeatable print volumes. A solder paste volume predictor model was developed from the data, and was used to aid stencil design involving fine-feature devices.

Figure 1. Effect of area ratio.

In the light of changes in solder-paste formulations that have improved fine-feature print capabilities, the need for new models was identified. A stencil-design option - individually stepped aperture pockets* - was introduced, and a project began to study the transfer efficiency of solder pastes using stepped stencils with 0.5-mm area-array devices. The study examines the effects of straight (naturally tapered) walls, stepped-down areas around devices, and individually stepped aperture pockets. All print data were taken on actual PCBs. Figure 2 shows the three aperture profiles.

Figure 2. Aperture profiles

An individually stepped aperture pocket is an individual step-down around each aperture, and concentric with it. Figure 3 illustrates a close-up cross-section (schematic) of the aperture. The clearance area around the device often limits a traditional step-down in a stencil. If the clearance area is insufficient, fill pressure of the squeegee can be compromised at the perimeter of the device. Stepped stencils may also be incompatible with enclosed print-head systems.

Experimental Method - Materials

The experiment used two fine-feature devices, two solder pastes, and three aperture profiles to measure the effects of each stencil design. The devices were 0.5-mm-pitch CSP 98 and BGA 56, and stencils were measured for actual squeegee-side and board-side aperture openings and foil thicknesses. A calculation was taken for actual aperture volumes. No-clean Type 3 tin/lead** and lead-free solder pastes*** were used, as were four stencil thicknesses: 3-, 4-, 5-, and 6-mil foils, each stepped as shown in Figure 4. The test vehicle used was an immersion-silver-finish CERF board with numerous sites for each device (Figure 5).

Figure 3. Individually stepped aperture

For each paste-stencil combination, the boards were numbered, cleaned, and reprinted, in sequence, to limit experimental error. They were printed at a speed of 4 in./sec., a print pressure of 1.25 lbs./in. of blade length, and a separation speed of 0.5 in./sec. The first four boards were discarded, then alternate prints were used for measurement so that all data taken came from a rear-to-front squeegee stroke. Blades were levelled after each stencil change, and stencils were wiped manually from the underside before each measured print. Solder paste deposit volumes were measured. For each paste-stencil combination, data were gathered from four boards, as shown in red in Figure 5. Data were analyzed for four BGAs and six CSPs from each print.

Volumes & Repeatability

Results for BGA 56 devices with 12-mil features show good repeatability (within ±10% of the standard deviation), for both tin/lead and lead-free pastes. The data also show that when printing 12-mil features, the most robust printing can be achieved by using straight (tapered) walls on 4-, 5-, and 6-mil foils. Although individually stepped aperture pockets provide slightly higher average volumes, the variability in the volumes also increases. When printing CSP 98 devices with 10-mil features, repeatability again was considered good (within ±15% of the standard deviation). Printing a 10-mil feature with a 5-mil foil (AR = 0.5) benefits from the use of a stepped-down area. In this case, average volumes are higher and standard deviations are lower.

Figure 4. Stencil design.

No benefit was shown when stepping down the entire device area to print 10-mil features with a 4-mil foil. However, there was some benefit to using individually stepped apertures. These showed improvements in average volumes for area ratios of 0.45-0.55, but in some cases they introduced variations. Although data were collected and analyzed for printing 10-mil features with a 6-mil foil, this practice is strongly discouraged.

Transfer-efficiency Model

Print performance of both pastes was nearly identical, so data were grouped, analyzed, and treated as a larger sample size. The regression model of transfer efficiencies showed a 0.4-1.0 area-ratio linearity range. The lowest area ratio tested was 0.4. Area ratios less than 0.5 are not recommended. Given any particular configuration of required stencil thickness and aperture diameter, the optimum stencil design and aperture profile can be predicted using the previous volume data. The equation that represents transfer efficiency for these pastes is:

Figure 5. CERF board

TE = SQRT [0.995-3.008*(1-AR)2]

In Figure 6, blue data points and the trend line represent the most recent tests, while red data points and the trend line represent the 2001 benchmark study. The current-generation pastes show better release characteristics throughout the entire area-ratio range. These pastes also exhibit a curve with a different shape that looks like the upper quadrant of a circle, whereas the previously generated curve was a polynomial S-shape. Therefore, the equation that models the circle has a different algebraic format than its predecessor. Regression analysis of the data produced an R value of 0.929, showing a high degree of correlation. Regression coefficients generated were: slope = -0.008, and Y-intercept = 0.995. Data and trend lines are shown in Figure 7.

Figure 6. Transfer efficiency comparison.

Transfer-efficiency models are only generated for straight (normal taper) apertures. No models for stepped or pocket apertures have been generated. It should also be noted that registration of this pocket aperture is critical.

Conclusion

Fine-feature print performances of lead-free and tin/lead solder pastes were nearly identical. The widespread notion that assemblers cannot expect lead-free pastes to print as well as tin/lead pastes is a myth.

Data generated in print tests can provide an easy reference to aid in stencil design and foil-thickness selection. Because the data was generated on a PCB in a production-type setting, similar results can be anticipated on the assembly line.

Figure 7. Transfer efficiency curve.

Transfer-efficiency models show definitive improvements in release characteristics of newer paste formulations, compared to previous tests. Individually stepped apertures can enhance transfer efficiency in specific situations where area ratios are very low. However, transfer-efficiency models have not yet been developed for this technology.

* MicroSteps, ALPHA, A Cookson Electronics company, Jersey City, N.J.** OM-5100 Sn63 solder paste, Cookson Electronics.*** OM-338 SAC 305 alloy, Cookson Electronics.

REFERENCES

1. Fleck, I., Chouta, P., “A New Dimension in Stencil Print Optimization,” SMTA International, Rosemont, Ill., September, 2002.

Grant Burkhalter, systems engineer, ALPHA, may be contacted at gburkhalter@cooksonelectronics.com. Esse Leak, process technician, may be contacted at eleak@ cooksonelectronics.com. Chrys Shea, R&D applications engineer, may be at cshea@ cooksonelectronics.com. Ron Tripp, quality engineer, may be contacted at rtripp@cooksonelectronics.com. Greg Wade, senior process engineer, may be contacted at gwade@cooksonelectronics.com.