Roadmap to BGA Standards

Estimated reading time: 6 minutes

Tracing the development of IPC-7095, Design and Assembly Process Implementation for BGAs. By Dieter Bergman

At a 1994 meeting of the Surface Mount Council (SMC), the subject of SMT standards was at the top of the agenda. Emerging technologies forced a discussion as to what was becoming standard protocol. The meeting revealed there was no definitive standard for the new technologies.

Meeting attendees discussed the latest technologies they were using, such as flip chip technology and chip scale packaging (CSP). The industry was debating whether to go toward finer pitch peripheral parts because 0.5 mm no longer was adequate. Some components were being prepared at 0.4, 0.3 and 0.25 mm. The form factor also did not lend itself to increasing input/outputs (I/O) without a great penalty in design and routability of the interconnecting conductors. Some felt that an array package offered more promise.

Increasing device complexity was a driving factor for SMT. To keep package size down, lead spacing was decreased to 1.27 and 0.63 mm. Further increases in active elements in very large-scale integration (VLSI) devices, such as the 32-bit microprocessor, required more than 100 I/Os and closer lead spacing. Closer spacing of leads on 0.4, 0.3 and 0.25 mm was an option. However, the array package format was becoming the favorite for high-pin-count devices.

The advent of array component packages made pitch more forgiving. Ball grid arrays (BGA) were standardized on 1.5, 1.25 and 1.0 mm pitch. I/Os clustered together permitted denser output patterns with larger assembly process windows than fine-pitch peripheral leaded parts. The via pattern for the board, however, required tighter feature control. Many industry electronic packaging schemes used devices with custom chip designs that created greater I/O needs. The complexity of custom-designed VLSI circuits increased the number of I/Os required. Some designs already used more than 300 I/O terminations.

The large pin count and finer pitch of some peripheral packages caused re-thinking of packaging style vs. assembly complexity. The concern in using these complex parts relates to board design and manufacturing issues. Design is concerned with interconnecting all the leads and having sufficient room for routing conductors; manufacturing is concerned with attaching all the leads to the mounting structure without bridging (shorts) or missing solder joints (opens).

Figure 1. Conductor routing methodology for BGA component land patterns.

With more circuit customization in silicon and package size increasing, printed circuit board (PCB) size also needed to change. However, higher I/O demands required multilayer or high-density interconnection (microvia) designs to support wiring needs for closely spaced devices, or to provide the escape routing from internal connections of array component patterns. Both PCB sides needed to be used to place all the components.

SMC Fosters New StandardsThe discussion at the 1994 SMC meeting led to the development of two important new standards. Council members agreed the standards should address issues involved with array vs. peripheral packaging, and direct chip attach (DCA) vs. CSP.

An outline was prepared and challenges were identified. Because the council represented several standardization bodies, the documents became joint standards. The two standards developed were J-STD-012, Implementation of Flip Chip and Chip Scale Technology, and J-STD-013, Implementation of Ball Grid Array and Other High Density Technology.

Complexity MatrixWith the advent of new integrated circuit (IC) package styles such as BGA, electronic equipment designers carefully reviewed their options. BGA immaturity gave way to data that indicated high-yield assembly processes and good field reliability reports. Positioning tolerances were more liberal; quality was achieved through process control instead of visual inspection. Additionally, flip chips and CSPs offered added density advantages for products that needed a smaller, lighter form factor.

Figure 2. A wire-bonded plastic BGA.

Tables 1 and 2 are complexity matrices that establish the parameters for high-pin-count and fine-pitch definitions. Developed by the J-STD-013 subcommittee, complexity is judged on a scale of 1 to 10, with 10 the most difficult. The first number in any of the matrix cells reflects design complexity. Some are simple; others are more difficult because of the number of I/Os that require interconnection. The second number in each matrix cell reflects the difficulty of manufacturing. Manufacturing includes testing the PCB or mounting structure and the completed assembly.

Table 1 shows the matrix for packaged parts with leads or terminations around the perimeter. Table 2 shows the relationship or evaluation of parts with their leads or terminations beneath the package in an array format.

Figure 3. A flip chip-bonded BGA.

Today, multilayer PCB technology is used in products to support fine-pitch, peripheral-leaded technology. For a 0.5 mm pitch, 208 I/O quad flat pack (QFP), the required wiring length is 113 cm/cm2. For a four-conductor/channel-design rule, seven conductive wiring signal layers are needed. In fact, because only a few fine-pitch devices are used, the average wiring demand is slightly less than 113 cm/cm2. The localized conductor routing demand is met by using more of the PCB or interconnecting structure surface.

The previous example is for peripheral-leaded packages using standard multilayer boards. The rules change dramatically when developing a redistribution layer for moving bonding sites on a bare die to an array pattern position. Additionally, the routing density for escapes from array devices' inside land pattern may not provide the traditional 1, 2, 3 or 4 conductor routing opportunity (Figure 1). High-density interconnect (HDI) technology plays a dramatic role in changing the wiring demand capability.

Defining Standardization RequirementsNeither J-STD-012 nor -013 are traditional standards. Each sets the stage for discussions as to what standards need to be developed for the infrastructure to take hold. In the early days, only companies with good technical resources could afford to embark on an unproven technology. Additionally, the industry also was outsourcing, so choosing the wrong partner could have proven to be disastrous.

Each J standard defined a development plan. The standards needed for implementation were identified and a scope and purpose were chosen. A unique number was assigned to each project without identifying what standards developing organization would take the leadership role. The resulting work could become J, IPC, Electronic Industries Alliance (EIA) or Joint Electronic Device Engineering Council (JEDEC) standards.

Table 3 shows the status of the 20 projects identified in the J-STD-012 (IEC PAS 62084). Table 4 shows the status of the 11 projects identified in the J-STD-013 (IEC PAS 62085). Each J standard coordinated by the SMC has been published by the International Electrotechnical Commission as a publicly available specification (PAS). PAS rules allow the standard developer to permit the international republication of the original document so experts in other countries can access the same information.

The Best is Yet to ComeA group of dedicated individuals just completed IPC-7095, Design and Assembly Process Implementation for BGAs. Under the leadership of Ray Prasad, experts from Celestica, Intel, Merix, Amkor, RadiSys, Tektronix, Micron and Glenbrook Technology developed a document that identifies all the requirements for implementing BGA technology.

IPC-7095 describes the design and assembly challenges for implementing BGA and fine-pitch BGA (FBGA) technology. The effect of BGA and FBGA on current technology and component types also is addressed. This document focuses on critical inspection, repair and reliability issues associated with BGAs.

The target audience for IPC-7095 is managers, design and process engineers, and operators and technicians dealing with the electronic assembly, inspection and repair processes. The intent is to provide useful and practical information to those using BGAs or considering implementation. The document provides insight as to how bare die are attached to substrates. Figures 2 and 3 show wire-bonded and flip chip configurations used in BGA manufacturing.

Figure 4. Example of voids in eutectic solder balls.

In addition to various product descriptions, IPC-7095 also provides information and discussion on voids in the BGA attachment structure. Figure 4 shows one example of X-ray used to determine void presence and size at the BGA ball interface.

For more IPC-7095 information, contact IPC's customer service department at (847) 790-5362. The industry is indebted to the hard work and contributions made by the individuals whose names are listed on the Acknowledgements page of each standard.

DIETER BERGMAN is director of technology transfer for the IPC -- Association Connecting Electronics Industries, 2215 Sanders Road, Northbrook, IL 60062; (847) 509-9700; Fax: (847) 509-9798.

*Pitch.** Not practical.